Memory Channel B - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Signal Description
Table 8. Memory Channel B (Sheet 1 of 2)
Signal Name
SB_BS[2:0]
SB_DM[7:0]
SB_DQS[8]
SB_DQS[7:0]
SB_DQS#[8]
SB_DQS#[7:0]
SB_DQ[71:64]
SB_DQ[63:0]
SB_MA[15:0]
SB_CK[1:0]
SB_CK#[1:0]
SB_CKE[1:0]
SB_CS#[1:0]
April 2010
Document Number: 323178-002
Bank Select: These signals define which banks
are selected within each SDRAM rank.
Write Enable Control Signal: Used with
SB_WE# SB_RAS# and SB_CAS# (along with SB_CS#) to
define the SDRAM Commands.
RAS Control Signal: Used with SB_CAS# and
SB_RAS# SB_WE# (along with SB_CS#) to define the SRAM
Commands.
CAS Control Signal: Used with SB_RAS# and
SB_CAS# SB_WE# (along with SB_CS#) to define the SRAM
Commands.
Data Mask: These signals are used to mask
individual bytes of data in the case of a partial
write, and to interrupt burst writes. When
activated during writes, the corresponding data
groups in the SDRAM are masked. There is one
SB_DM[7:0] for every data byte lane.
ECC Data Strobe: SB_DQS[8] is the data strobe
for the ECC check data bits SB_DQ[71:64]
Note: Not required for non-ECC mode
Data Strobes: SB_DQS[7:0] and its complement
signal group make up a differential strobe pair. The
data is captured at the crossing point of
SB_DQS[7:0] and its SB_DQS#[7:0] during read
and write transactions.
ECC Data Strobe Complement: SB_DQS#[8] is
the complement strobe for the ECC check data bits
SB_DQ[71:64]
Note: Not required for non-ECC mode
Data Strobe Complements: These are the
complementary strobe signals.
ECC Check Data Bits: SB_DQ[71:64] are the ECC
check data bits for Channel B
Note: Not required for non-ECC mode
Data Bus: Channel B data signal interface to the
SDRAM data bus.
Memory Address: These signals are used to
provide the multiplexed row and column address
to the SDRAM.
SDRAM Differential Clock: Channel B SDRAM
Differential clock signal pair. The crossing of the
positive edge of SB_CK and the negative edge of
its complement SB_CK# are used to sample the
command and control signals on the SDRAM.
SDRAM Inverted Differential Clock: Channel B
SDRAM Differential clock signal-pair complement.
Clock Enable: (1 per rank) Used to:
- Initialize the SDRAMs during power-up.
- Power-down SDRAM ranks.
- Place all SDRAM ranks into and out of self-refresh
during STR.
Chip Select: (1 per rank) Used to select particular
SDRAM components during the active state. There
is one Chip Select for each SDRAM rank.
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Description
® ®
Celeron Processor P4500, P4505 Series
Direction/Buffer
Type
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
Datasheet Addendum
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