Intel I5-520E - DATASHEET ADDENDUM Datasheet page 4

6.2.10 SBUSN6 - Secondary Bus Number.............................................................91
6.2.11 SUBUSN6 - Subordinate Bus Number ........................................................92
6.2.12 IOBASE6 - I/O Base Address ....................................................................92
6.2.13 IOLIMIT6 - I/O Limit Address ...................................................................93
6.2.14 SSTS6 - Secondary Status .......................................................................94
6.2.15 MBASE6 - Memory Base Address...............................................................95
6.2.16 MLIMIT6 - Memory Limit Address ..............................................................96
6.2.17 PMBASE6 - Prefetchable Memory Base Address ...........................................97
6.2.18 PMLIMIT6 - Prefetchable Memory Limit Address ..........................................98
6.2.19 PMBASEU6 - Prefetchable Memory Base Address Upper................................99
6.2.20 PMLIMITU6 - Prefetchable Memory Limit Address Upper ............................. 100
6.2.21 CAPPTR6 - Capabilities Pointer................................................................ 101
6.2.22 INTRLINE6 - Interrupt Line .................................................................... 101
6.2.23 INTRPIN6 - Interrupt Pin........................................................................ 102
6.2.24 BCTRL6 - Bridge Control ........................................................................ 102
6.2.25 PM_CAPID6 - Power Management Capabilities .......................................... 104
6.2.26 PM_CS6 - Power Management Control/Status ........................................... 105
6.2.27 SS_CAPID - Subsystem ID and Vendor ID Capabilities ............................... 107
6.2.28 SS - Subsystem ID and Subsystem Vendor ID .......................................... 107
6.2.29 MSI_CAPID - Message Signaled Interrupts Capability ID ............................ 108
6.2.30 MC - Message Control............................................................................ 108
6.2.31 MA - Message Address........................................................................... 110
6.2.32 MD - Message Data ............................................................................... 110
6.2.33 PEG_CAPL - PCI Express-G Capability List ................................................ 111
6.2.34 PEG_CAP - PCI Express-G Capabilities ..................................................... 111
6.2.35 DCAP - Device Capabilities ..................................................................... 112
6.2.36 DCTL - Device Control ........................................................................... 113
6.2.37 DSTS - Device Status ............................................................................ 114
6.2.38 LCAP - Link Capabilities ......................................................................... 115
6.2.39 LCTL - Link Control ............................................................................... 118
6.2.40 LSTS - Link Status ................................................................................ 120
6.2.41 SLOTCAP - Slot Capabilities.................................................................... 122
6.2.42 SLOTCTL - Slot Control .......................................................................... 123
6.2.43 SLOTSTS - Slot Status........................................................................... 126
6.2.44 RCTL - Root Control .............................................................................. 128
6.2.45 RSTS - Root Status ............................................................................... 129
6.2.46 LCTL2 - Link Control 2 ........................................................................... 129
6.2.47 LSTS2 - Link Status 2............................................................................ 131
6.2.48 PEGLC - PCI Express-G Legacy Control .................................................... 132
6.3 PCI Device 6 - Extended Configuration................................................................ 133
6.3.1 VCECH - Virtual Channel Enhanced Capability Header ................................ 133
6.3.2 PVCCAP1 - Port VC Capability Register 1 .................................................. 133
6.3.3 PVCCAP2 - Port VC Capability Register 2 .................................................. 134
6.3.4 PVCCTL - Port VC Control....................................................................... 135
6.3.5 VC0RCAP - VC0 Resource Capability ........................................................ 135
6.3.6 VC0RCTL - VC0 Resource Control ............................................................ 136
6.3.7 VC0RSTS - VC0 Resource Status............................................................. 137
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
4
® ®
Celeron Processor P4500, P4505 Series
April 2010
Document Number: 323178-002