Pci Device 6 Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
Reserved and Preserved:
1. Reserved for future RW implementations; software must preserve value read for
writes to bits.
2. Reserved and Zero: Reserved for future R/WC/S implementations; software must
use 0 for writes to bits.
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are
part of the Reserved and Preserved type, which have historically been the typical
definition for Reserved.
It is important to note that most (if not all) control bits in this device cannot be
modified unless the link is down. Software is required to first Disable the link, then
program the registers, and then re-enable the link (which will cause a full-retrain with
the new settings).
Table 23. PCI Device 6 Register (Sheet 1 of 3)
Register Name
Vendor VID6
Identification
Device DID6
Identification
PCI Command PCICMD6
PCI Status PCISTS6
Revision RID6
Identification
Class Code CC6
Cache Line Size CL6
Header Type HDR6
Primary Bus PBUSN6
Number
Secondary Bus SBUSN6
Number
Subordinate Bus SUBUSN6
Number
I/O Base Address IOBASE6
I/O Limit Address IOLIMIT6
Secondary Status SSTS6
Memory Base MBASE6
Address
Memory Limit MLIMIT6
Address
Prefetchable PMBASE6
Memory Base
Address
April 2010
Document Number: 323178-002
Register
Register Start
Symbol
0
2
4
6
8
9
C
E
18
19
1A
1C
1D
1E
20
22
24
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Register End Default Value
1 8086h
3 0047h
5 0000h
7 0010h
8 10h
B 060400h
C 00h
E 01h
18 00h
19 00h
1A 00h
1C F0h
1D 00h
1F 0000h
21 FFF0h
23 0000h
25 FFF1h
® ®
Celeron Processor P4500, P4505 Series
Access
RO
RO
RO; RW
RO; RWC
RO
RO
RW
RO
RO
RW
RW
RO; RW
RO; RW
RWC; RO
RO; RW
RO; RW
RO; RW
Datasheet Addendum
81