Intel I5-520E - DATASHEET ADDENDUM Datasheet page 124

Table 65. SLOTCTL - Slot Control Register (Sheet 2 of 3)
Bit Access Default
Value
12 RO
11 RO
10 RO
9:8 RO
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
124
RST/
PWR
0b Core Reserved for Data Link Layer State Changed Enable
(DLLSCE)
If the Data Link Layer Link Active capability is implemented,
when set to 1b, this field enables software notification when Data
Link Layer Link Active field is changed.
If the Data Link Layer Link Active capability is not implemented,
this bit is permitted to be read-only with a value of 0b.
0b Core Reserved for Electromechanical Interlock Control (EIC)
If an Electromechanical Interlock is implemented, a write of 1b
to this field causes the state of the interlock to toggle. A write of
0b to this field has no effect. A read to this register always
returns a 0.
0b Core Reserved for Power Controller Control (PCC)
If a Power Controller is implemented, this field when written sets
the power state of the slot per the defined encodings. Reads of
this field must reflect the value from the latest write, even if the
corresponding hot-plug command is not complete, unless
software issues a write without waiting for the previous
command to complete in which case the read value is undefined.
Depending on the form factor, the power is turned on/off either
to the slot or within the adapter. Note that in some cases the
power controller may autonomously remove slot power or not
respond to a power-up request based on a detected fault
condition, independent of the Power Controller Control setting.
The defined encodings are:
0b Power On
1b Power Off
If the Power Controller Implemented field in the Slot Capabilities
register is set to 0b, then writes to this field have no effect and
the read value of this field is undefined.
00b Core Reserved Power Indicator Control (PIC)
If a Power Indicator is implemented, writes to this field set the
Power Indicator to the written state. Reads of this field must
reflect the value from the latest write, even if the corresponding
hot-plug command is not complete, unless software issues a
write without waiting for the previous command to complete in
which case the read value is undefined.
00:Reserved
01:On
10:Blink
11:Off
If the Power Indicator Present bit in the Slot Capabilities register
is 0b, this field is permitted to be read-only with a value of 00b.
®
Celeron
Processor Configuration Registers
Description
®
Processor P4500, P4505 Series
April 2010
Document Number: 323178-002