Peglc - Pci Express-G Legacy Control; Peglc - Pci Express-G Legacy Control Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Table 70. LSTS2 - Link Status 2 Register (Sheet 2 of 2)
0 RO
6.2.48

PEGLC - PCI Express-G Legacy Control

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Controls functionality that is needed by Legacy (non-PCI Express aware) OS's during
run time.
Table 71.

PEGLC - PCI Express-G Legacy Control Register

Bit Access
31:3 RO 00000000h
2 RW
1 RW
0 RW
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
132
0b Core
Default RST/
Value PWR
Core Reserved
0b Core PME GPE Enable (PMEGPE)
0 = Do not generate GPE PME message when PME is received.
1 = Generate a GPE PME message when PME is received. This
0b Core Hot-Plug GPE Enable (HPGPE)
0 = Do not generate GPE Hot-Plug message when Hot-Plug
1 = Generate a GPE Hot-Plug message when Hot-Plug Event is
0b Core General Message GPE Enable (GENGPE)
0 = Do not forward received GPE assert/deassert messages.
1 = Forward received GPE assert/deassert messages.
®
Celeron
Current De-emphasis Level (CURDELVL):
Current De-emphasis Level –
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s speed, this bit is
0b.
0/6/0/PCI
EC-EFh
00000000h
RO; RW
32 bits
Description
enables the processor to support PMEs on the PEG port
under legacy OSs.
event is received.
received. This enables the processor to support Hot-Plug
on the PEG port under legacy OSs
®
Processor P4500, P4505 Series
Processor Configuration Registers
April 2010
Document Number: 323178-002