Rsts - Root Status; Lctl2 - Link Control 2; Rsts - Root Status Register; Lctl2 - Link Control 2 Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
6.2.45

RSTS - Root Status

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Provides information about PCI Express Root Complex specific parameters.
Table 68.

RSTS - Root Status Register

Default
Bit Access
31:18 RO
17 RO
16 RWC
15:0 RO
6.2.46

LCTL2 - Link Control 2

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Table 69. LCTL2 - Link Control 2 Register (Sheet 1 of 3)
Bit Access
15:13 RO
April 2010
Document Number: 323178-002
RST/
Value PWR
0000h Core Reserved and Zero (RSVD)
For future R/WC/S implementations; software must use 0 for
writes to bits.
0b Core PME Pending (PMEP)
Indicates that another PME is pending when the PME Status bit
is set. When the PME Status bit is cleared by software; the PME
is delivered by hardware by setting the PME Status bit again
and updating the Requestor ID appropriately. The PME pending
bit is cleared by hardware if no more PMEs are pending.
0b Core PME Status (PMES)
Indicates that PME was asserted by the requestor ID indicated
in the PME Requestor ID field. Subsequent PMEs are kept
pending until the status register is cleared by writing a 1 to this
field.
0000h Core PME Requestor ID (PMERID)
Indicates the PCI requestor ID of the last PME requestor.
Default RST/
Value PWR
000b Core
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
0/6/0/PCI
C0-C3h
00000000h
RO; RWC
32 bits
Description
0/6/0/PCI
D0-D1h
0001h
RO; RW-S; RW;
16 bits
Description
Reserved (RSVD):
®
Celeron
®
Processor P4500, P4505 Series
Datasheet Addendum
129