Errcmd - Error Command - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
Table 16. Error Status Register (Sheet 2 of 2)
Bit
1
0
6.1.3

ERRCMD - Error Command

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the Processor responses to various system errors. Since the
Processor does not have an SERRB signal, SERR messages are passed from the
Processor to the PCH over DMI.
When a bit in this register is set, a SERR message will be generated on DMI whenever
the corresponding flag is set in the ERRSTS register. The actual generation of the SERR
message is globally enabled for Device #0 via the PCI Command register.
April 2010
Document Number: 323178-002
Access Default
Value
RW1C-S 0b
RW1C-S 0b
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
RST/
PWR
Core Multiple-bit DRAM ECC Error Flag
(DMERR):
If this bit is set to 1, a memory read data
transfer had an uncorrectable multiple-bit error.
When this bit is set, the column, row, bank, and
rank that caused the error, and the error
syndrome, are logged in the ECC Error Log
register in the channel where the error
occurred. Once this bit is set, the
CxECCERRLOG fields are locked until the CPU
clears this bit by writing a 1. Software uses bits
[1:0] to detect whether the logged error
address is for a Single-bit or a Multiple-bit
error.
This bit is reset on PWROK.
Core Single-bit DRAM ECC Error Flag (DSERR):
If this bit is set to 1, a memory read data
transfer had a single-bit correctable error and
the corrected data was returned to the
requesting agent. When this bit is set the
column, row, bank, and rank where the error
occurred and the syndrome of the error are
logged in the ECC Error Log register in the
channel where the error occurred. Once this bit
is set the CxECCERRLOG fields are locked to
further single-bit error updates until the CPU
clears this bit by writing a 1. A multiple bit error
that occurs after this bit is set will overwrite the
CxECCERRLOG fields with the multiple-bit error
signature and the DMERR bit will also be set. A
single bit error that occurs after a multibit error
will set this bit but will not overwrite the other
fields.
This bit is reset on PWROK.
0/0/0/PCI
CA-CBh
0000h
RO; RW;
16 bits
®
Celeron
Description
®
Processor P4500, P4505 Series
Datasheet Addendum
73