Pm_Capid6 - Power Management Capabilities; Pm_Capid6 - Power Management Capabilities Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

6.2.25

PM_CAPID6 - Power Management Capabilities

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Table 48.

PM_CAPID6 - Power Management Capabilities Register

Default
Bit Access
31:27 RO
26 RO
25 RO
24:22 RO
21 RO
20 RO
19 RO
18:16 RO
15:8 RO
7:0 RO
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
104
RST/
Value PWR
19h Core PME Support (PMES)
This field indicates the power states in which this device may
indicate PME wake via PCI Express messaging. D0, D3hot &
D3cold. This device is not required to do anything to support
D3hot & D3cold, it simply must report that those states are
supported. Refer to the latest PCI Power Management
Specification for encoding explanation and other power
management details.
0b Core D2 Power State Support (D2PSS)
hard wired to 0 to indicate that the D2 power management
state is NOT supported.
0b Core D1 Power State Support (D1PSS)
hard wired to 0 to indicate that the D1 power management
state is NOT supported.
000b Core Auxiliary Current (AUXC)
hard wired to 0 to indicate that there are no 3.3Vaux auxiliary
current requirements.
0b Core Device Specific Initialization (DSI)
hard wired to 0 to indicate that special initialization of this
device is NOT required before generic class device driver is to
use it.
0b Core Auxiliary Power Source (APS)
hard wired to 0.
0b Core PME Clock (PMECLK)
hard wired to 0 to indicate this device does NOT support PMEB
generation.
011b Core PCI PM CAP Version (PCIPMCV)
Version - A value of 011b indicates that this function complies
with the latest revision of the PCI Power Management Interface
Specification.
90h Core Pointer to Next Capability (PNC)
This contains a pointer to the next item in the capabilities list. If
MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the
capabilities list is the Message Signaled Interrupts (MSI)
capability at 90h. If MSICH (CAPL[0] @ 7Fh) is 1, then the next
item in the capabilities list is the PCI Express capability at A0h.
01h Core Capability ID (CID)
Value of 01h identifies this linked list item (capability structure)
as being for PCI Power Management registers.
®
Celeron
Processor Configuration Registers
0/6/0/PCI
80-83h
C8039001h
RO
32 bits
Description
®
Processor P4500, P4505 Series
April 2010
Document Number: 323178-002