Pvcctl - Port Vc Control; Vc0Rcap - Vc0 Resource Capability; Pvccap2 - Port Vc Capability Register 2 - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
Table 75.

PVCCAP2 - Port VC Capability Register 2

Bit Access
31:24 RO
23:8 RO
7:0 RO

6.3.4PVCCTL - Port VC Control

B/D/F/Type:0/6/0/MMR
Address Offset:10C-10Dh
Default Value:0000h
Access: RO; RW;
Size:16 bits
Table 76.

PVCCTL - Port VC Control

Bit Access
15:4 RO
3:1 RW
0 RO

6.3.5VC0RCAP - VC0 Resource Capability

B/D/F/Type:0/6/0/MMR
Address Offset:110-113h
Default Value:00000001h
Access: RO;
Size:32 bits
Table 77. VC0RCAP - VC0 Resource Capability (Sheet 1 of 2)
Bit Access
31:24 RO
23 RO
April 2010
Document Number: 323178-002
Default
RST/PWR
Value
00h Core
0000h Core
00h Core
Default
RST/PWR
Value
000h Core
000b Core
0b Core
Default
RST/PWR
Value
00h Core
0b Core
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Description
VC Arbitration Table Offset (VCATO):
Indicates the location of the VC Arbitration Table. This
field contains the zero-based offset of the table in
DQWORDS (16 bytes) from the base address of the
Virtual Channel Capability Structure. A value of 0
indicates that the table is not present (due to fixed VC
priority).
Reserved
Reserved for VC Arbitration Capability (VCAC)
Description
Reserved
VC Arbitration Select (VCAS)
This field is programmed by software to the only possible
value as indicated in the VC Arbitration Capability field.
Since there is no other VC supported than the default,
this field is reserved.
Reserved for Load VC Arbitration Table
Used for software to update the VC Arbitration Table when
VC arbitration uses the VC Arbitration Table. As a VC
Arbitration Table is never used by this component this
field will never be used.
Description
Reserved for Port Arbitration Table Offset
Reserved
®
Celeron
®
Processor P4500, P4505 Series
Datasheet Addendum
135