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Processor Configuration Registers
Table 78.
VC0RCTL - VC0 Resource Control
Bit
Access
31
RO
30:27
RO
26:24
RO
23:20
RO
19:17
RW
16
RO
15:8
RO
7:1
RW
0
RO
6.3.7
VC0RSTS - VC0 Resource Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Reports the Virtual Channel specific status.
April 2010
Document Number: 323178-002
Default
RST/PWR
Value
1b
Core
0h
Core
000b
Core
0h
Core
000b
Core
0b
Core
00h
Core
7Fh
Core
1b
Core
®
TM
Intel
Core
i7-620LE/UE, i7-610E, i5-520E and Intel
Description
VC0 Enable (VC0E):
For VC0 this is hard wired to 1 and read only as VC0 can
never be disabled.
Reserved
VC0 ID (VC0ID):
Assigns a VC ID to the VC resource. For VC0 this is hard
wired to 0 and read only.
Reserved
Port Arbitration Select (PAS):
Port Arbitration Select – This field configures the VC
resource to provide a particular Port Arbitration service.
This field is valid for RCRBs, Root Ports that support peer
to peer traffic, and Switch Ports, but not for PCI Express
Endpoint devices or Root Ports that do not support peer to
peer traffic. The permissible value of this field is a number
corresponding to one of the asserted bits in the Port
Arbitration Capability field of the VC resource.
Reserved
Reserved for Load Port Arbitration Table ():
Reserved
TC/VC0 Map (TCVC0M):
Indicates the TCs (Traffic Classes) that are mapped to the
VC resource. Bit locations within this field correspond to
TC values. For example, when bit 7 is set in this field, TC7
is mapped to this VC resource. When more than one bit in
this field is set, it indicates that multiple TCs are mapped
to the VC resource. In order to remove one or more TCs
from the TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions with the
TC labels are targeted at the given Link.
TC0/VC0 Map (TC0VC0M):
Traffic Class 0 is always routed to VC0.
0/6/0/MMR
11A-11Bh
0002h
RO;
16 bits
®
Celeron
®
Processor P4500, P4505 Series
Datasheet Addendum
137
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