Intel I5-520E - DATASHEET ADDENDUM Datasheet page 117

Processor Configuration Registers
Table 61. LCAP - Link Capabilities Register (Sheet 3 of 3)
Default
Bit Access
Value
17:15 RW-O 010b
14:12 RO 100b
11:10 RW-O
9:4 RW-O
3:0 RW-O
April 2010
Document Number: 323178-002
RST/
PWR
Core L1 Exit Latency (L1ELAT)
Indicates the length of time this Port requires to complete the
transition from L1 to L0.
000: Less than 1us
001: 1 us to less than 2 us
010: 2 us to less than 4 us
011: 4 us to less than 8 us
100: 8 us to less than 16 us
101: 16 us to less than 32 us
110: 32 us-64 us
111: More than 64 us
BIOS Requirement: If this field is required to be any value other
than the default, BIOS must initialize it accordingly.
Both bytes of this register that contain a portion of this field must
be written simultaneously in order to prevent an intermediate
(and undesired) value from ever existing.
Core L0s Exit Latency (L0SELAT)
Indicates the length of time this Port requires to complete the
transition from L0s to L0.
000:Less than 64 ns
001:64 ns to less than 128 ns
010:128 ns to less than 256 ns
011:256 ns to less than 512 ns
100:512 ns to less than 1 µs
101:1 µs to less than 2 µs
110:2 µs - 4 µs
111:More than 4 µs
The actual value of this field depends on the common Clock
Configuration bit (LCTL[6]) register.
11b Core Active State Link PM Support (ASLPMS)
ASPM L0s and L1 supported.
08h Core Max Link Width (MLW)
Indicates the maximum number of lanes supported for this link.
1h Core Max Link Speed (MLS)
Supported Link Speed – This field indicates the supported Link
speed(s) of the associated Port.
Defined encodings are:
0001b2.5-GT/s Link speed supported
All other encodings are reserved.
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Description
® ®
Celeron Processor P4500, P4505 Series
Datasheet Addendum
117