Dcap - Device Capabilities; Dcap - Device Capabilities Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Table 57. PEG_CAP - PCI Express-G Capabilities Register
Default
Bit Access
3:0 RO
6.2.35

DCAP - Device Capabilities

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Indicates PCI Express device capabilities.
Table 58.

DCAP - Device Capabilities Register

Default
Bit Access
Value
31:16 RO 0000h
15 RO
14:6 RO
5 RO
4:3 RO
2:0 RO
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
112
RST/
Value PWR
2h Core PCI Express Capability Version (PCIECV)
hard wired to 2h to indicate compliance to the PCI Express
Capabilities Register Expansion ECN.
RST/
PWR
Core Reserved
Not Applicable or Implemented. Hard wired to 0.
1b Core Role-Based Error Reporting (RBER)
Indicates that this device implements the functionality defined
in the Error Reporting ECN as required by the PCI Express Base
spec.
000h Core Reserved
Not Applicable or Implemented. Hard wired to 0.
0b Core Extended Tag Field Supported (ETFS)
hard wired to indicate support for 5-bit Tags as a Requestor.
00b Core Phantom Functions Supported (PFS)
Not Applicable or Implemented. Hard wired to 0.
000b Core Max Payload Size (MPS)
hard wired to indicate 128B max supported payload for
Transaction Layer Packets (TLP).
®
Celeron
Processor Configuration Registers
Description
0/6/0/PCI
A4-A7h
00008000h
RO
32 bits
Description
®
Processor P4500, P4505 Series
April 2010
Document Number: 323178-002