Intel I5-520E - DATASHEET ADDENDUM Datasheet page 28

Processor Ball and Signal Information
® TM
Figure 5. Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
(Top View, Upper-Left Quadrant)
71 70 69 68 67 66 65
DC_TES DC_TES DC_TES
BV
VSS
T_BV71 T_BV69 T_BV68
SB_DM[6
BU
]
DC_TES DC_TES
BT
VSS
T_BT71 T_BT69
DC_TES SB_DQ[5
BR
VSS VSS
T_BR71 0]
BP
SB_DQ[5 SA_DQ[5
BN
VSS
4] 0]
BM
VSS
SB_DQ[5
BL
VSS
5]
SB_DQ[6 SB_DQ[6
BK
0] 1]
SB_DQ[5 SB_DQS SA_DQ[6
BJ
6] [7] 0]
BH
VSS
SB_DQ[5 SB_DQS
BG
8] #[7]
SB_DQ[5 SB_DM[7 SA_DQ[6
BF
7] ] 1]
BE
RSVD VSS RSVD VSS
SB_DQ[6 SB_DQ[6
BD
2] 3]
SA_DQ[6 SB_DQ[5
BC
3] 9]
SA_DQ[5
BB
VSS RSVD
9]
BA
VSS
AY
VSS RSVD VSS
AW
RSVD VSS
PM_EXT
AV
RSVD RSVD
_TS#[0]
AU
RSVD VSS RSVD
AT
RSVD RSVD
AR
RSVD RSVD
AP
VSS RSVD
GFX_VID
AN
RSVD
[4]
GFX_VID GFX_VID
AM
RSVD
[6] [5]
GFX_DP GFX_IM
AL
RSLPVR ON
AK
RSVD VSS RSVD RSVD
AJ
VSS
GFX_VID GFX_VR
AH
RSVD
[3] _EN
GFX_VID GFX_VID
AG
[2] [1]
GFX_VID
AF
VSS
[0]
AE
VSS COMP0
AD
COMP3 COMP1
AC
RSVD COMP2 RSVD VSS
AB
VSS
323178-002
64 63 62 61 60 59 58 57
SB_DQS SB_DQ[4 SB_DQ[4 SB_DM[5
VSS
[6] 8] 7] ]
SB_DQS SB_DQ[4
VSS VSS
#[6] 6]
SB_DQ[5 SB_DQ[4 SB_DQ[4
3] 2] 3]
SB_DQ[5 SB_DQ[5
1] 2]
SB_DQ[4 SA_DQS
9] #[6]
SA_DM[6 SA_DQ[4
VSS
] 9]
SA_DQS[
6]
VSS
SA_DQ[5 SA_DQ[5
VSS VSS
4] 5]
SA_DQ[5 SA_DQ[5 SA_DQ[5
VSS
6] 1] 3]
SA_DM[7
VSS
]
SA_DQ[5 SA_DQ[5
VSS VTT0 VTT0
7] 2]
SA_DQS[ SA_DQS
7] #[7]
VTT0 VTT0 VSS
SA_DQ[5
VSS VTT0 VTT0 VSS
8]
SA_DQ[6
VSS VTT0 VSS VCAP0
2]
VSS VTT0 VSS VCAP0
PM_EXT
_TS#[1]
VSS VTT0 VTT0 VSS
VSS
VSS VTT0 VTT0 VSS
VSS
VSS VTT0 VTT0 VCAP0
VSS
VSS VTT0 VTT0 VCAP0
VSS VCAP2 VCAP2 VCAP2 VCAP0
VSS VCAP2 VCAP2 VSS
VSS
VSS VCAP2 VCAP2 VCC
VSS
VSS VCAP2 VCAP2 VSS
VSS
VSS VCAP2 VCAP2 VSS
® ®
Celeron Processor P4500, P4505 Series Ballmap
56 55 54 53 52 51 50 49
SB_DQS SB_DQ[3 SB_DQ[3 SB_DQ[3
#[5] 9] 7] 4]
SB_DQS SB_DQ[4 SB_ODT
VSS VSS
[5] 1] [1]
SB_DQ[4 SB_DQ[3 SB_DQS SB_DQS
4] 8] [4] #[4]
SB_DQ[4 SB_DQ[4 SB_DQ[3
5] 0] 5]
SA_DQ[4 SA_DQ[4
7] 1]
SA_DQ[4
VSS
6]
VSS
SA_DQS
VSS
#[5]
SA_DQ[4
3]
SA_DQ[4 SA_DQS[
VSS
2] 5]
SA_DM[5
VSS
]
SA_DQ[4
8]
VCAP0 VSS VCAP0 VSS
VCAP0 VSS VCAP0 VSS
VSS VCAP0 VSS VCAP0
VSS VCAP0 VSS VCAP0
VCAP0 VSS VCAP0 VSS
VCAP0 VSS VCAP0 VSS
VSS VCAP0 VSS VCAP0
VSS VCAP0 VSS VCAP0
VSS VCAP0 VSS VCAP0
VSS VSS VSS VSS
VCC VCC VCC VCC
VCC VSS VCC VSS
VCC VSS VCC VSS
48 47 46 45 44 43 42 41
SB_DQ[3 SB_DM[4 SB_ODT SB_BS[1 SB_BS[0
3] ] [0] ] ]
SB_CAS SB_MA[1
VSS VSS
# 0]
SB_DQ[3 SB_DQ[3 SB_MA[1 SB_CS#[
SB_WE#
2] 6] 3] 1]
SB_CS#[
VSS
0]
SA_DQ[4 SA_DQ[3 SA_DQ[3
0] 9] 8]
SA_DQ[3
VSS
3]
SA_ODT[
VSS
1]
SA_DQS[ SA_CAS
4] #
SA_DQ[4 SA_CS#[
5] 1]
SA_DQ[4 SA_DQS SA_DQ[3
VSS
4] #[4] 7]
SA_DM[4 SA_DQ[7
] 0]
SA_DQ[3 SA_DQ[3 SA_ODT[
5] 4] 0]
VCAP0 VSS VCAP1 VSS VCAP1
VCAP0 VSS VCAP1 VSS VCAP1
VSS VCAP1 VSS VCAP1 VSS
VSS VCAP1 VSS VCAP1 VSS
VCAP0 VSS VCAP1 VSS VCAP1
VCAP0 VSS VCAP1 VSS VCAP1
VSS VCAP1 VSS VCAP1 VSS
VSS VCAP1 VSS VCAP1 VSS
VSS VCAP1 VSS VCAP1 VSS
VSS VSS VSS VSS VSS
VCC VCC VCC VCC VCC
VCC VSS VCC VSS VCC
VCC VSS VCC VSS VCC
40 39 38 37 36
SM_RCO SB_CK[1 SA_MA[2
MP[2] ] ]
SA_DQ[6 SB_CK#[
VSS
6] 1]
SB_RAS SA_MA[0
SA_BS[0]
# ]
SM_RCO
MP[1]
SA_DQ[3 SB_DQ[6
6] 8]
SA_RAS
VSS
#
SA_CK#[
1]
SA_DQ[3 SA_DQ[7
2] 1]
SA_CS#[ SA_CK[1
SA_BS[1]
0] ]
VSS
SA_MA[1
SA_WE#
3]
VSS VCAP1
VSS VCAP1
VCAP1 VSS
VCAP1 VSS
VSS VCAP1
VSS VCAP1
VCAP1 VSS
VCAP1 VSS
VCAP1 VSS
VSS VSS
VTT0 VTT0
VTT0 VTT0
VSS VSS
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