C1Wrdatactrl - Channel 1 Write Data Control; C1Eccerrlog - Channel 1 Ecc Error Log; Channel 1 Write Data Control Registers - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
6.1.7

C1WRDATACTRL - Channel 1 Write Data Control

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
Table 21.

Channel 1 Write Data Control Registers

Bit
23:16
15
14:0
6.1.8

C1ECCERRLOG - Channel 1 ECC Error Log

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is used to store the error status information in ECC enabled
configurations, along with the error syndrome and the rank/bank/row/column address
information of the address block of main memory of which an error (single bit or multi-
bit error) has occurred. Note that the address fields represent the address of the first
single or the first multiple bit error occurrence after the error flag bits in the ERRSTS
register have been cleared by software. A multiple bit error will overwrite a single bit
error. Once the error flag bits are set as a result of an error, this bit field is locked and
doesn't change as a result of a new error until the error flag is cleared by software.
Same is the case with error syndrome field, but the following priority needs to be
followed if more than one error occurs on one or more of the 4 QWs. MERR on QW0
MERR on QW1 MERR on QW2 MERR on QW3 CERR on QW0 CERR on QW1 CERR on
QW2 CERR on QW3.
April 2010
Document Number: 323178-002
Default
Access
Value
RW 00h
RW 0b
RW 4110h
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
0/0/0/MCHBAR
64D-64Fh
004111h
RW
24 bits
00h
RST/
PWR
Core ECC bit invert vector (C1sd_cr_eccbitinv):
This vector operates individually for every ECC
bit in the selected 64b ECC block, during write
to DRAM. For all k between 0 and 7, when
bit(k) is set to 1, the value for the k ECC bit
(which corresponds with k data byte lane) is
inverted. Otherwise, the value for the k ECC bit
is not affected.
Core ECC Diagnostic Enable
(C1sd_cr_eccdiagen):
1: The ECC bit invert vector is used to invert
selected ECC bits, during writes to DRAM.
0: The diagnostic feature is turned off.
Core Reserved
0/0/0/MCHBAR
680 -687h
0000000000000000h
RO; RO-V-S
64 bits
®
Celeron
Description
®
Processor P4500, P4505 Series
Datasheet Addendum
79