Intel I5-520E - DATASHEET ADDENDUM Datasheet page 88

Table 27. PCISTS6 - PCI Status Register (Sheet 2 of 2)
Bit Access Default
Value
5 RO
4 RO
3 RO
2:0 RO 000b
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
88
RST/
PWR
0b Core 66-/60-MHz Capability (CAP66)
Not Applicable or Implemented. Hard wired to 0.
1b Core Capabilities List (CAPL)
Indicates that a capabilities list is present. Hard wired to 1.
0b Core INTA Status (INTAS)
Indicates that an interrupt message is pending internally to the
device. Only PME and Hot Plug sources feed into this status bit
(not PCI INTA-INTD assert and deassert messages). The INTA
Assertion Disable bit, PCICMD6[10], has no effect on this bit.
Note that INTA emulation interrupts received across the link are
not reflected in this bit.
Core Reserved
®
Celeron
Processor Configuration Registers
Description
®
Processor P4500, P4505 Series
April 2010
Document Number: 323178-002