Intel I5-520E - DATASHEET ADDENDUM Datasheet page 86

Table 26. PCICMD6 - PCI Command Register (Sheet 2 of 2)
Bit Access Default
6 RW
5 RO
4 RO
3 RO
2 RW
1 RW
0 RW
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Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
86
RST/
Value PWR
0b Core Parity Error Response Enable (PERRE)
Controls whether or not the Master Data Parity Error bit in the
PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register CANNOT
1 = Master Data Parity Error bit in PCI Status register CAN be
0b Core VGA Palette Snoop (VGAPS)
Not Applicable or Implemented. Hard wired to 0.
0b Core Memory Write and Invalidate Enable (MWIE)
Not Applicable or Implemented. Hard wired to 0.
0b Core Special Cycle Enable (SCE)
Not Applicable or Implemented. hard wired to 0.
0b Core Bus Master Enable (BME)
Controls the ability of the PEG port to forward Memory and IO
Read/Write Requests in the upstream direction.
0 = This device is prevented from making memory or IO
1 = This device is allowed to issue requests to its primary bus.
0b Core Memory Access Enable (MAE)
0 = All of Device 6's memory space is disabled.
1 = Enable the Memory and Pre-fetchable memory address
0b Core IO Access Enable (IOAE)
0 = All of Device 6's I/O space is disabled.
1 = Enable the I/O address range defined in the IOBASE6, and
®
Celeron
Description
be set.
set.
requests to its primary bus. Note that according to the PCI
Local Bus Specification, as MSI interrupt messages are in-
band memory writes, disabling the bus master enable bit
prevents this device from generating MSI interrupt
messages or passing them from its secondary bus to its
primary bus. Upstream memory writes/reads, IO writes/
reads, peer writes/reads, and MSIs will all be treated as
illegal cycles. Writes are forwarded to memory address
C0000h with byte enables deasserted. Reads is forwarded
to memory address C0000h and will return Unsupported
Request status (or Master abort) in its completion packet.
Completions for previously issued memory read requests
on the primary bus is issued when the data is available.
This bit does not affect forwarding of Completions from the
primary interface to the secondary interface.
ranges defined in the MBASE6, MLIMIT6, PMBASE6, and
PMLIMIT6 registers.
IOLIMIT6 registers.
®
Processor P4500, P4505 Series
Processor Configuration Registers
April 2010
Document Number: 323178-002