Subusn6 - Subordinate Bus Number; Iobase6 - I/O Base Address; Subusn6 - Subordinate Bus Number Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

6.2.11

SUBUSN6 - Subordinate Bus Number

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express-G. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express-G.
Table 34.

SUBUSN6 - Subordinate Bus Number Register

Default
Bit Access
Value
7:0 RW
6.2.12

IOBASE6 - I/O Base Address

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express-G I/O access routing based on the
following formula:
IO_BASE=< address =<IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are treated as 0. Thus the bottom of the defined I/O address range is aligned
to a 4-KB boundary.
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
92
RST/
PWR
00h Core Subordinate Bus Number (BUSN)
This register is programmed by configuration software with the
number of the highest subordinate bus that lies behind the Device
6 bridge. When only a single PCI device resides on the PCI
Express-G segment, this register will contain the same value as
the SBUSN6 register.
®
Celeron
Processor Configuration Registers
0/6/0/PCI
1Ah
00h
RW
8 bits
Description
0/6/0/PCI
1Ch
F0h
RO; RW
8 bits
®
Processor P4500, P4505 Series
April 2010
Document Number: 323178-002