Mlimit6 - Memory Limit Address; Mlimit6 - Memory Limit Address Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

6.2.16

MLIMIT6 - Memory Limit Address

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express-G non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE=< address =<MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be
FFFFFh. Thus, the top of the defined memory address range is at the top of a 1-MB
aligned memory block.
Note: Memory range covered by MBASE and MLIMIT registers are used to map non-
prefetchable PCI Express-G address ranges (typically where control/status memory-
mapped I/O data structures of the graphics controller will reside) and PMBASE and
PMLIMIT are used to map prefetchable address ranges (typically graphics local
memory). This segregation allows application of USWC space attribute to be performed
in a true plug-and-play manner to the prefetchable address range for improved CPU-
PCI Express memory access performance.
Note also that configuration software is responsible for programming all address range
registers (prefetchable, non-prefetchable) with the values that provide exclusive
address ranges, i.e., prevent overlap with each other and/or with the ranges covered
with the main memory. There is no provision in the processor hardware to enforce
prevention of overlap and operations of the system in the case of overlap are not
guaranteed.
Table 39.

MLIMIT6 - Memory Limit Address Register

Default
Bit Access
Value
15:4 RW 000h
3:0 RO
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
96
RST/
PWR
Core Memory Address Limit (MLIMIT)
Corresponds to A[31:20] of the upper limit of the address range
passed to PCI Express-G.
0h Core Reserved
®
Celeron
Processor Configuration Registers
0/6/0/PCI
22-23h
0000h
RO; RW
16 bits
Description
®
Processor P4500, P4505 Series
April 2010
Document Number: 323178-002