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11.6.6
Procedure for processing errors that occurred during UART (UART0, UART1, UART2, UART3)
communication
The procedure for processing errors that occurred during UART (UART0, UART1, UART2, UART3) communication
is described in Figures 13-91 and 13-92.
Figure 11-91. Processing Procedure in Case of Parity Error or Overrun Error
Software Manipulation
Reads SDRmn register.
Reads SSRmn register.
Writes SIRmn register.
Figure 11-92. Processing Procedure in Case of Framing Error
Software Manipulation
Reads SDRmn register.
Reads SSRmn register.
Writes SIRmn register.
Sets STmn bit to 1.
Synchronization with other party of
communication
Sets SSmn bit to 1.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 12 13
CHAPTER 11 SERIAL ARRAY UNIT
Hardware Status
The BFF0 = 0, and channel n is
enabled to receive data.
Error flag is cleared.
Hardware Status
The BFF = 0, and channel n is enabled
to receive data.
Error flag is cleared.
The SEmn = 0, and channel n stops
operating.
The SEmn = 1, and channel n is
enabled to operate.
User's Manual U17854EJ9V0UD
Remark
This is to prevent an overrun error if the
next reception is completed during error
processing.
Error type is identified and the read
value is used to clear error flag.
Only error generated at the point of
reading can be cleared, by writing the
value read from the SSRmn register to
the SIRmn register without modification.
Remark
This is to prevent an overrun error if the
next reception is completed during error
processing.
Error type is identified and the read
value is used to clear error flag.
Only error generated at the point of
reading can be cleared, by writing the
value read from the SSRmn register to
the SIRmn register without modification.
Synchronization with the other party of
communication is re-established and
communication is resumed because it is
considered that a framing error has
occurred because the start bit has been
shifted.
449
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