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(2) DMA operation control register n (DRCn)
DRCn is a register that is used to enable or disable transfer of DMA channel n.
Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1).
DRCn can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 14-5. Format of DMA Operation Control Register n (DRCn)
Address: FFFBCH (DRC0), FFFBDH (DRC1)
Symbol
<7>
DRCn
DENn
DENn
0
1
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
DSTn
0
1
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
When a software trigger (STGn) or the start source trigger set by IFCn3 to IFCn0 is input, DMA transfer is started.
When DMA transfer is completed after that, this bit is automatically cleared to 0.
Write 0 to this bit to forcibly terminate DMA transfer under execution.
Caution The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is terminated
without waiting for generation of the interrupt (INTDMAn) of DMAn, therefore, set DSTn to 0
and then DENn to 0 (for details, refer to 14.5.7 Forcible termination by software).
Remark
n: DMA channel number (n = 0, 1)
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CHAPTER 14 DMA CONTROLLER
After reset: 00H
6
5
0
0
Disables operation of DMA channel n (stops operating cock of DMA).
Enables operation of DMA channel n.
DMA transfer of DMA channel n is completed.
DMA transfer of DMA channel n is not completed (still under execution).
User's Manual U17854EJ9V0UD
R/W
4
3
2
0
0
0
DMA operation enable flag
DMA transfer mode flag
1
<0>
0
DSTn
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