Acknowledge (Ack) - NEC 78K0R/KE3 User Manual

IICX0 IICCL0
Bit 0 Bit 3 Bit 1
CLX0 SMC0 CL01
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 1
0 1 1
×
1 0
1 1 0
1 1 1
1 1 1
Caution Determine the transfer clock frequency of I
enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change
the transfer clock frequency, clear IICE0 once to 0.
Remarks 1. ×:
don't care
2. f : CPU/peripheral hardware clock frequency
CLK

12.5.5 Acknowledge (ACK)

ACK is used to check the status of serial data at the transmission and reception sides.
The reception side returns ACK each time it has received 8-bit data.
The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception
side, it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been
detected can be checked by using bit 2 (ACKD0) of IIC status register 0 (IICS0).
When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a
slave does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops
transmission. If ACK is not returned, the possible causes are as follows.
<1> Reception was not performed normally.
<2> The final data item was received.
<3> The reception side specified by the address does not exist.
To generate ACK, the reception side makes the SDA0 line low at the ninth clock (indicating normal reception).
Automatic generation of ACK is enabled by setting bit 2 (ACKE0) of IIC control register 0 (IICC0) to 1. Bit 3 (TRC0)
of the IICS0 register is set by the data of the eighth bit that follows 7-bit address information. Usually, set ACKE0 to 1
for reception (TRC0 = 0).
If a slave can receive no more data during reception (TRC0 = 0) or does not require the next data item, then the
slave must inform the master, by clearing ACKE0 to 0, that it will not receive any more data.
When the master does not require the next data item during reception (TRC0 = 0), it must clear ACKE0 to 0 so that
ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any
more data (transmission will be stopped).
CHAPTER 12 SERIAL INTERFACE IIC0
Table 12-3. Selection Clock Setting
Transfer Clock (f /m)
CLK
Bit 0
CL00
0 f /88
CLK
1 f /172
CLK
0 f /344
CLK
1 f /44
CLK
×
f /48
CLK
0 f /96
CLK
1 f /24
CLK
×
Setting prohibited
×
f /48
CLK
0 Setting prohibited
1 f /24
CLK
User's Manual U17854EJ9V0UD
Settable Selection Clock
(f ) Range
CLK
4.00 MHz to 8.4 MHz Normal mode (SMC0 bit = 0)
8.38 MHz to 16.76 MHz
16.76 MHz to 20 MHz
2.00 MHz to 4.2 MHz
7.60 MHz to 16.76 MHz Fast mode (SMC0 bit = 1)
16.00 MHz to 20 MHz
4.00 MHz to 8.4 MHz
8.00 MHz to 8.38 MHz Fast mode (SMC0 bit = 1)
16.00 MHz to 16.76 MHz
4.00 MHz to 4.19 MHz
2
C by using CLX0, SMC0, CL01, and CL00 before
Operation Mode
495