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Figure 12-6. Format of IIC Control Register 0 (IICC0) (2/4)
Note 1
SPIE0
Enable/disable generation of interrupt request when stop condition is detected
0
Disable
1
Enable
Condition for clearing (SPIE0 = 0)
• Cleared by instruction
• Reset
Note 1
WTIM0
0
Interrupt request is generated at the eighth clock's falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
1
Interrupt request is generated at the ninth clock's falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of
this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is
inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local
address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) is issued. However, when
the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 = 0)
• Cleared by instruction
• Reset
Notes 1, 2
ACKE0
0
Disable acknowledgment.
1
Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level.
Condition for clearing (ACKE0 = 0)
• Cleared by instruction
• Reset
Notes 1. The signal of this bit is invalid while IICE0 is 0. Set this bit during that period.
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledgment is
generated regardless of the set value.
CHAPTER 12 SERIAL INTERFACE IIC0
Condition for setting (SPIE0 = 1)
• Set by instruction
Control of wait and interrupt request generation
Condition for setting (WTIM0 = 1)
• Set by instruction
Acknowledgment control
Condition for setting (ACKE0 = 1)
• Set by instruction
User's Manual U17854EJ9V0UD
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