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Function
Details of
Function
Low-
LVIM:Low-
voltage
Voltage
detector
detection
register
LVIS: Low-
voltage detection
level select
register
Used as reset
(when detecting
level of supply
voltage (V
(LVIOFF = 1)
Used as reset
(when detecting
level of supply
voltage (V
(LVIOFF = 0)
Used as reset
(when detecting
level of input
voltage from
external input pin
(EXLVI))
848
APPENDIX B LIST OF CAUTIONS
When LVI is used in interrupt mode (LVIMD = 0) and LVISEL is set to 0, an interrupt
request signal (INTLVI) that disables LVI operation (clears LVION) when the supply
voltage (V
) is less than or equal to the detection voltage (V
DD
voltage of external input pin (EXLVI) is less than or equal to the detection voltage
(V
)) is generated and LVIIF may be set to 1.
EXLVI
Be sure to clear bits 4 to 7 to "0".
Change the LVIS value with either of the following methods.
• When changing the value after stopping LVI
<1> Stop LVI (LVION = 0).
<2> Change the LVIS register.
<3> Set to the mode used as an interrupt (LVIMD = 0).
<4> Mask LVI interrupts (LVIMK = 1).
<5> Enable LVI operation (LVION = 1).
<6> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
because an LVIIF flag may be set when LVI operation is enabled.
• When changing the value after setting to the mode used as an interrupt (LVIMD =
0)
<1> Mask LVI interrupts (LVIMK = 1).
<2> Set to the mode used as an interrupt (LVIMD = 0).
<3> Change the LVIS register.
<4> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
because an LVIIF flag may be set when the LVIS register is changed.
When an input voltage from the external input pin (EXLVI) is detected, the detection
voltage (V
) is fixed. Therefore, setting of LVIS is not necessary.
EXLVI
<1> must always be executed.
immediately after the processing in <4>.
If supply voltage (V
DD
))
reset signal is not generated.
DD
Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
))
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
DD
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
<1> must always be executed.
immediately after the processing in <3>.
If input voltage from external input pin (EXLVI) ≥ detection voltage (V
(TYP.)) when LVIMD is set to 1, an internal reset signal is not generated.
Input voltage from external input pin (EXLVI) must be EXLVI < V
User's Manual U17854EJ9V0UD
Cautions
When LVIMK = 0, an interrupt may occur
) ≥ detection voltage (V
) when LVIMD is set to 1, an internal
LVI
When LVIMK = 0, an interrupt may occur
(24/33)
Page
p.633
) (if LVISEL = 1, input
LVI
p.634
p.635
p.635
p.637
p.637
p.639
μ
s
p.641
= 1.21 V
p.641
EXLVI
.
p.641
DD
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