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(7) Operation speed mode control register (OSMC)
This register is used to control the step-up circuit of the flash memory for high-speed operation.
If the microcontroller operates at a low speed with a system clock of 10 MHz or less, the power consumption can
be lowered by setting this register to the default value, 00H.
OSMC can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F00F3H
Symbol
OSMC
<R>
CHAPTER 5 CLOCK GENERATOR
Figure 5-8. Format of Operation Speed Mode Control Register (OSMC)
After reset: 00H
R/W
7
6
0
0
FSEL
0
Operates at a frequency of 10 MHz or less (default).
1
Operates at a frequency higher than 10 MHz.
Cautions 1. OSMC can be written only once after reset release, by an 8-bit memory
manipulation instruction.
2. Write "1" to FSEL before the following two operations.
• Changing the clock prior to dividing f
• Operating the DMA controller.
3. The CPU waits when "1" is written to the FSEL flag.
Interrupt requests issued during a wait will be suspended.
The wait time is 16.6
= f
/2.
IH
However, counting the oscillation stabilization time of f
the CPU is waiting.
4. To increase f
or more clocks have elapsed.
5. Flash memory can be used at a frequency of 10 MHz or lower if FSEL is 1.
5
4
3
0
0
0
f
frequency selection
CLK
μ
μ
s to 18.5
s when f
to 10 MHz or higher, set FSEL to "1", then change f
CLK
User's Manual U17854EJ9V0UD
2
1
0
0
to a clock other than f
CLK
μ
= f
, and 33.3
s to 36.9
CLK
IH
can continue even while
X
0
FSEL
.
IH
μ
s when f
CLK
after two
CLK
153
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