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Figure 11-71. Example of Contents of Registers for UART Transmission of UART
(d) Serial output level register m (SOLm) ... Sets only the bits of the target channel.
15
14
13
SOL0
0
0
15
14
13
SOL1
0
0
(e) Serial mode register mn (SMRmn)
15
14
13
SMRmn
CKSmn
CCSmn
0/1
0
(f) Serial communication operation setting register mn (SCRmn)
15
14
13
SCRmn
TXEmn
RXEmn
DAPmn
1
0
0
(g) Serial data register mn (SDRmn) (lower 8 bits: TXDq)
15
14
13
SDRmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 12,
q: UART number (q = 0, 1, 3)
: Setting is fixed in the UART transmission mode,
0/1: Set to 0 or 1 depending on the usage of the user
422
CHAPTER 11 SERIAL ARRAY UNIT
(UART0, UART1, UART3) (2/2)
12
11
10
9
0
0
0
0
0
12
11
10
9
0
0
0
0
0
12
11
10
9
0
0
0
0
0
12
11
10
9
CKPmn
EOCmn
PTCmn1
0
0
0
0/1
Setting of parity bit
00B: No parity
01B: 0 parity
10B: Even parity
11B: Odd parity
12
11
10
9
Baud rate setting
User's Manual U17854EJ9V0UD
8
7
6
5
0
0
0
0
0
0: Forward (normal) transmission
1: Reverse transmission
8
7
6
5
0
0
0
0
0
0: Forward (normal) transmission
1: Reverse transmission
8
7
6
5
4
STSmn
SISmn0
0
0
0
1
0
8
7
6
5
4
PTCmn0
DIRmn
SLCmn1
SLCmn0
0/1
0/1
0
0/1
0/1
8
7
6
5
Transmit data setting
0
: Setting disabled (set to the initial value)
4
3
2
1
0
SOL02
SOL00
0
0/1
0
0/1
4
3
2
1
0
SOL12
0
0/1
0
0
3
2
1
0
MDmn2
MDmn1
MDmn0
0
0
1
0/1
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
3
2
1
0
DLSmn2
DLSmn1
DLSmn0
0
1
0/1
0/1
Setting of stop bit
01B: Appending 1 bit
10B: Appending 2 bits
4
3
2
1
0
TXDq
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