NEC 78K0R/KE3 User Manual page 224

Figure 6-38. Operation Procedure of Interval Timer/Square Wave Output Function
TAU
default
setting
Sets the TAU0EN bit of the PER0 register to 1.
Sets the TPS0 register.
Determines clock frequencies of CK00 and CK01.
Channel Sets the TMR0n register (determines operation mode of
default channel).
setting Sets the TIS0n bit to 1 (f
the count clock.
Sets interval (period) value to the TDR0n register.
To use the TO0k output
Clears the TOM0k bit of the TOM0 register to 0 (toggle
mode).
Clears the TOL0k bit to 0.
Sets the TO0k bit and determines default level of the
TO0k output.
Sets TOE0k to 1 and enables operation of TO0k.
Clears the port register and port mode register to 0.
Operation Sets TOE0k to 1 (only when operation is resumed).
start Sets the TS0n bit to 1.
The TS0n bit automatically returns to 0 because it is a
trigger bit.
During Set values of the TMR0n register, TOM0n, and TOL0n
operation bits cannot be changed.
Set value of the TDR0n register can be changed.
The TCR0n register can always be read.
The TSR0n register is not used.
Set values of the TO0 and TOE0 registers can be
changed.
The TT0n bit is set to 1.
Operation
The TT0n bit automatically returns to 0 because it is a
stop
trigger bit.
TOE0k is cleared to 0 and value is set to TO0k bit.
To hold the TO0k pin output level
TAU stop
Clears TO0k bit to 0 after the value to
be held is set to the port register.
When holding the TO0k pin output level is not necessary
Switches the port mode register to input mode.
The TAU0EN bit of the PER0 register is cleared to 0.
Remark n = 0 to 7, k = 0 to 6
224
CHAPTER 6 TIMER ARRAY UNIT
Software Operation
/4) when f /4 is selected as
SUB SUB
User's Manual U17854EJ9V0UD
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TO0k pin goes into Hi-Z output state.
The TO0k default setting level is output when the port mode
register is in the output mode and the port register is 0.
TO0k does not change because channel stops operating.
The TO0k pin outputs the TO0k set level.
TE0n = 1, and count operation starts.
Value of TDR0n is loaded to TCR0n at the count clock
input. INTTM0n is generated and TO0k performs toggle
operation if the MD0n0 bit of the TMR0n register is 1.
Counter (TCR0n) counts down. When count value reaches
0000H, the value of TDR0n is loaded to TCR0n again and the
count operation is continued. By detecting TCR0n = 0000H,
INTTM0n is generated and TO0k performs toggle operation.
After that, the above operation is repeated.
TE0n = 0, and count operation stops.
TCR0n holds count value and stops.
The TO0k output is not initialized but holds current status.
The TO0k pin outputs the TO0k set level.
The TO0k pin output level is held by port function.
The TO0k pin output level goes into Hi-Z output state.
Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TO0k bit is cleared to 0 and the TO0k pin is set to port
mode.)