NEC 78K0R/KE3 User Manual page 488

(5) IIC clock select register 0 (IICCL0)
This register is used to set the transfer clock for the I
IICCL0 can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are
read-only. The SMC0, CL01, and CL00 bits are set in combination with bit 0 (CLX0) of IIC function expansion
register 0 (IICX0) (see 12.5.4 Transfer clock setting method).
Set IICCL0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0.
Reset signal generation clears this register to 00H.
Address: FFF54H After reset: 00H
Symbol 7
IICCL0 0
CLD0
0
1
Condition for clearing (CLD0 = 0)
• When the SCL0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
DAD0
0
1
Condition for clearing (DAD0 = 0)
• When the SDA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
SMC0
0
1
DFC0
0
1
Digital filter can be used only in fast mode.
In fast mode, the transfer clock does not vary regardless of DFC0 bit set (1)/clear (0).
The digital filter is used for noise elimination in fast mode.
Note Bits 4 and 5 are read-only.
Remark
488
CHAPTER 12 SERIAL INTERFACE IIC0
Figure 12-9. Format of IIC Clock Select Register 0 (IICCL0)
Note
R/W
6 <5> <4>
0 CLD0 DAD0
Detection of SCL0 pin level (valid only when IICE0 = 1)
The SCL0 pin was detected at low level.
The SCL0 pin was detected at high level.
Detection of SDA0 pin level (valid only when IICE0 = 1)
The SDA0 pin was detected at low level.
The SDA0 pin was detected at high level.
Operates in standard mode.
Operates in fast mode.
Digital filter operation control
Digital filter off.
Digital filter on.
IICE0: Bit 7 of IIC control register 0 (IICC0)
User's Manual U17854EJ9V0UD
2
C bus.
<3> <2>
SMC0 DFC0
Condition for setting (CLD0 = 1)
• When the SCL0 pin is at high level
Condition for setting (DAD0 = 1)
• When the SDA0 pin is at high level
Operation mode switching
1 0
CL01 CL00