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Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
(1) When LVI is OFF upon power application (option byte: LVIOFF = 1)
Supply voltage
(V
)
DD
V
LVI
Note 1
1.8 V
V
= 1.59 V (TYP.)
POC
0.5 V/ms (MIN.)
0 V
Wait for oscillation
accuracy stabilization
Internal high-speed
oscillation clock (f
)
IH
Starting oscillation is
High-speed
specified by software.
system clock (f
)
MX
(when X1 oscillation
is selected)
Reset processing
Wait for voltage
Operation
stabilization
CPU
stops
1.92 to 6.17 ms
Internal reset signal
The operation guaranteed range is 1.8 V ≤ V
Notes 1.
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
2.
If the rate at which the voltage rises to 1.8 V after power application is slower than 0.5 V/ms (MIN.),
input a low level to the RESET pin before the voltage reaches to 1.8 V, or set LVI to ON by default by
using an option byte (option byte: LVIOFF = 0).
3.
The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
4.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
5.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 20
LOW-VOLTAGE DETECTOR).
Remark V
: LVI detection voltage
LVI
V
: POC detection voltage
POC
626
CHAPTER 19 POWER-ON-CLEAR CIRCUIT
and Low-Voltage Detector (1/2)
Set LVI to be
Set LVI to be
used for reset
used for interrupt
Note 2
Wait for oscillation
Note 3
accuracy stabilization
Normal operation
Reset period
(internal high-speed
(oscillation
Note 5
oscillation clock)
stop)
Reset processing (43 to 160 s)
User's Manual U17854EJ9V0UD
Wait for oscillation
Note 4
accuracy stabilization
Starting oscillation is
Starting oscillation is
specified by software.
specified by software.
Reset processing
Normal operation
Reset period
(internal high-speed
Wait for voltage
(oscillation
Note 5
oscillation clock)
stabilization
stop)
μ
1.92 to 6.17 ms
≤ 5.5 V. To make the state at lower than 1.8 V reset
DD
Set LVI to be
used for reset
Note 3
Normal operation
(internal high-speed
Note 5
oscillation clock)
Operation stops
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