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Instruction
Mnemonic
Operands
Group
8-bit data
XCH
A, ES:!addr16
transfer
A, ES:[DE]
A, ES:[DE + byte]
A, ES:[HL]
A, ES:[HL + byte]
A, ES:[HL + B]
A, ES:[HL + C]
ONEB
A
X
B
C
saddr
!addr16
ES:!addr16
CLRB
A
X
B
C
saddr
!addr16
ES:!addr16
MOVS
[HL + byte], X
ES:[HL + byte], X
16-bit
MOVW
rp, #word
data
saddrp, #word
transfer
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
sfrp, AX
AX, rp
rp, AX
Notes 1.
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2.
When the program memory area is accessed.
3.
Except rp = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum.
CHAPTER 26 INSTRUCTION SET
Table 26-5. Operation List (4/17)
Bytes
Clocks
Note 1 Note 2
−
5
3
−
3
3
−
4
3
−
3
3
−
4
3
−
3
3
−
3
3
−
1
1
−
1
1
−
1
1
−
1
1
−
2
1
−
3
1
−
4
2
−
1
1
−
1
1
−
1
1
−
1
1
−
2
1
−
3
1
−
4
2
−
3
1
−
4
2
−
3
1
−
4
1
−
4
1
−
2
1
−
2
1
−
2
1
−
2
1
−
Note 3
1
1
−
Note 3
1
1
User's Manual U17854EJ9V0UD
Operation
A ←→ (ES, addr16)
A ←→ (ES, DE)
A ←→ ((ES, DE) + byte)
A ←→ (ES, HL)
A ←→ ((ES, HL) + byte)
A ←→ ((ES, HL) + B)
A ←→ ((ES, HL) + C)
A ← 01H
X ← 01H
B ← 01H
C ← 01H
(saddr) ← 01H
(addr16) ← 01H
(ES, addr16) ← 01H
A ← 00H
X ← 00H
B ← 00H
C ← 00H
(saddr) ← 00H
(addr16) ← 00H
(ES,addr16) ← 00H
(HL + byte) ← X
(ES, HL + byte) ← X
rp ← word
(saddrp) ← word
sfrp ← word
AX ← (saddrp)
(saddrp) ← AX
AX ← sfrp
sfrp ← AX
AX ← rp
rp ← AX
) selected by the system clock control
CLK
Flag
Z AC CY
×
×
×
×
691
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