Slave Reception - NEC 78K0R/KE3 User Manual

11.5.5 Slave reception

Slave reception is that the 78K0R/KE3 receives data from another device in the state of a transfer clock being input
from another device.
3-Wire Serial I/O
Target channel Channel 0 of SAU0
Pins used SCK00, SI00
Interrupt INTCSI00
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag Overrun error detection flag (OVF0n) only
Transfer data length 7 or 8 bits
Transfer rate Max. f
Data phase Selectable by DAP0n bit
• DAP0n = 0: Data input starts from the start of the operation of the serial clock.
• DAP0n = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase Selectable by CKP0n bit
• CKP0n = 0: Forward
• CKP0n = 1: Reverse
Data direction MSB or LSB first
Notes 1. Because the external serial clock input to pins SCK00 and SCK10 is sampled internally and used, the
fastest transfer rate is f
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 27
PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remarks 1. f : Operation clock (MCK) frequency of target channel
MCK
2. n: Channel number (n = 0, 2)
CHAPTER 11 SERIAL ARRAY UNIT
CSI00
Notes 1, 2
/6 [Hz]
MCK
/6 [Hz].
MCK
User's Manual U17854EJ9V0UD
CSI10
Channel 2 of SAU0
SCK10, SI10
INTCSI10
ELECTRICAL SPECIFICATIONS (STANDARD
401