Table of Contents
Advertisement
FFEFFH
Register bank 0
FFEF8H
Register bank 1
FFEF0H
Register bank 2
FFEE8H
Register bank 3
FFEE0H
FFEFFH
Register bank 0
FFEF8H
Register bank 1
FFEF0H
Register bank 2
FFEE8H
Register bank 3
FFEE0H
66
CHAPTER 3 CPU ARCHITECTURE
Figure 3-16. Configuration of General-Purpose Registers
(a) Function name
15
(b) Absolute name
15
User's Manual U17854EJ9V0UD
16-bit processing
HL
DE
BC
AX
0
16-bit processing
RP3
RP2
RP1
RP0
0
8-bit processing
H
L
D
E
B
C
A
X
7
0
8-bit processing
R7
R6
R5
R4
R3
R2
R1
R0
7
0
Advertisement
Table of Contents
