Master Reception - NEC 78K0R/KE3 User Manual

11.5.2 Master reception

Master reception is that the 78K0R/KE3 outputs a transfer clock and receives data from other device.
3-Wire Serial I/O
Target channel
Pins used
Interrupt
<R>
Error detection flag
Transfer data length
Transfer rate
Data phase
Clock phase
Data direction
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 27
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remark n: Channel number (n = 0, 2)
376
CHAPTER 11 SERIAL ARRAY UNIT
CSI00
Channel 0 of SAU0
SCK00, SI00
INTCSI00
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Overrun error detection flag (OVF0n) only
7 or 8 bits
/(2 × 2
Max. f /4 [Hz], Min. f
CLK CLK
Selectable by DAP0n bit
• DAP0n = 0: Data input starts from the start of the operation of the serial clock.
• DAP0n = 1: Data input starts half a clock before the start of the serial clock operation.
Selectable by CKP0n bit
• CKP0n = 0: Forward
• CKP0n = 1: Reverse
MSB or LSB first
ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
User's Manual U17854EJ9V0UD
Channel 2 of SAU0
SCK10, SI10
INTCSI10
× 128) [Hz]
11 Note
f : System clock frequency
CLK
CSI10