Stop Condition Generation - NEC 78K0R/KE3 User Manual

16-bit single-chip microcontrollers
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11.7.4 Stop condition generation

After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is
released.
(1) Processing flow
ST02
SE02
SOE02
Note
SCL10 output
SDA10 output
Note During the receive operation, the SOE02 bit is set to 0 before receiving the last data.
CHAPTER 11 SERIAL ARRAY UNIT
Figure 11-103. Timing Chart of Stop Condition Generation
SO02 bit
Operation
manipulation
stop
Figure 11-104. Flowchart of Stop Condition Generation
Completion of data
transmission/data reception
Starting generation of stop condition.
Writing 1 to ST02 bit to clear
(SE02 is cleared to 0)
Writing 0 to SOE02 bit
Writing 0 to SO02 bit
Writing 1 to CKO02 bit
Writing 1 to SO02 bit
End of IIC communication
User's Manual U17854EJ9V0UD
CKO02 bit
SO02 bit
manipulation
manipulation
Stop condition
Secure a wait time so that the specifications of
Wait
2
I
C on the slave side are satisfied.
463

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