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<2> Setting the internal high-speed oscillation clock as the source clock of the CPU/peripheral hardware clock
and setting the division ratio of the set clock (CKC register)
MCM0
0
Caution If switching the CPU/peripheral hardware clock from the high-speed system clock to the
internal high-speed oscillation clock after restarting the internal high-speed oscillation
clock, do so after 10
If the switching is made immediately after the internal high-speed oscillation clock is
restarted, the accuracy of the internal high-speed oscillation cannot be guaranteed for
μ
10
(3) Example of setting procedure when stopping the internal high-speed oscillation clock
The internal high-speed oscillation clock can be stopped in the following two ways.
• Executing the STOP instruction
• Setting HIOSTOP to 1
(a) To execute a STOP instruction
<1> Setting of peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, see CHAPTER 17 STANDBY FUNCTION).
<2> Setting the X1 clock oscillation stabilization time after STOP mode is released
If the X1 clock oscillates before the STOP mode is entered, set the value of the OSTS register before
executing the STOP instruction.
<3> Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and internal high-
speed oscillation clock is stopped.
(b) To stop internal high-speed oscillation clock by setting HIOSTOP to 1
<1> Confirming the CPU clock status (CKC register)
Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed
oscillation clock.
When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so
change the CPU clock to the high-speed system clock or subsystem clock.
CLS
MCS
0
0
1
168
CHAPTER 5 CLOCK GENERATOR
MDIV2
MDIV1
MDIV0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
μ
s or more have elapsed.
s.
0
Internal high-speed oscillation clock
1
High-speed system clock
×
Subsystem clock
User's Manual U17854EJ9V0UD
Selection of CPU/Peripheral
Hardware Clock (f
f
IH
f
/2
IH
2
f
/2
IH
3
f
/2
IH
4
f
/2
IH
5
f
/2
IH
CPU Clock Status
)
CLK
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