Transfer Clock Setting Method - NEC 78K0R/KE3 User Manual

12.5.4 Transfer clock setting method

(1) Selection clock setting method on the master side
2
The I C transfer clock frequency (f
= 1/(m × T + t
f
SCL
m = 24, 44, 48, 88, 96, 172, 344 (see Table 12-3 Selection Clock Setting)
T: 1/f
CLK
t : SCL0 rise time
R
t : SCL0 fall time
F
2
For example, the I C transfer clock frequency (f
is calculated using following expression.
= 1/(88 × 238.7 ns + 200 ns + 50 ns) ≅ 47.0 kHz
f
SCL
SCL0
SCL0
The selection clock is set using a combination of bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock select
register 0 (IICCL0) and bit 0 (CLX0) of IIC function expansion register 0 (IICX0).
(2) Selection clock setting method on the slave side
To use as slave, set the bits 3, 1, and 0 (SMC0, CL01, CL00) of the IIC clock selection register (IICL0) and the
bit 0 (CLX0) of the IIC function expansion register 0 (IICX0) according to the f
Range) and IIC Operation Mode (Normal or Fast ) as defined in Table 12-3. Selection Clock Setting.
494
CHAPTER 12 SERIAL INTERFACE IIC0
) is calculated using the following expression.
SCL
+ t )
R F
SCL
m × T + t
m/2 × T
t
R
inversion SCL0
User's Manual U17854EJ9V0UD
) when f = 4.19 MHz, m = 88, t
CLK
+ t
R F
t m/2 × T
F
inversion SCL0 inversion
= 200 ns, and t = 50 ns
R F
(Selectable Selection Clock
CLK