NEC 78K0R/KE3 User Manual page 872

Edition
8th edition Addition of expanded-specification products,
78F1145A, 78F1146A
Addition of (A) grade products of expanded-specification products,
78F1143A(A), 78F1144A(A), 78F1145A(A), 78F1146A(A)
Change of related documents
Addition of 1.1 Differences Between Conventional-Specification Products
μ
( PD78F114x) and Expanded-Specification Products (
Addition of Caution 4 to 1.5 Pin Configuration (Top View)
Modification of 1.7 Block Diagram
Change of description in 2.2.12 AV
Change of description in 2.2.14 RESET
Change of pins in Table 2-3 Connection of Unused Pins
Addition of Note to Figures 3-1 to 3-5
Change of figure in Remark of 3.1 Memory Space
Change of description in 3.1.1 (1) Vector table area
Change of description in 3.1.2 Mirror area
Change of description and addition and change of Caution in 3.1.3 Internal data
memory space
Addition of Cautions to 3.2.1 (3) Stack pointer (SP)
Modification of Table 3-5 SFR List
Addition of Caution 4 to Figure 4-33 Format of A/D Port Configuration Register
(ADPC)
Change of Cautions 3 and 5 in Figure 5-8 Format of Operation Speed Mode
Control Register (OSMC)
Change of Figure 5-13 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1))
Change of Figure 5-14 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Enabled Is Set (Option Byte:
LVIOFF = 0)) and description of <1>
Change of 5.6.3 (1) <1> Setting P123/XT1 and P124/XT2 pins (CMC register)
Change of and deletion of Note in Figure 5-15 CPU Clock Status Transition
Diagram
Change of Table 5-6 Maximum Time Required for Main System Clock Switchover
Change of channel number in 6.1.1 (4) Divider function
Change of description of CCS0n bit in Figure 6-6 Format of Timer Mode Register
0n (TMR0n)
Change of description in 6.4.3 (1) Changing values set in registers TO0, TOE0,
TOL0, and TOM0 during timer operation
Addition of description to 6.7.1 (1) Interval timer
Change of Figure 6-35 Block Diagram of Operation as Interval Timer/Square
Wave Output
Addition of (2) When f
Set Contents of Registers During Operation as Interval Timer/Square Wave
Output
Change of Figure 6-38 Operation Procedure of Interval Timer/Square Wave
Output Function
872
APPENDIX C REVISION HISTORY
Description
μ
PD78F1142A, 78F1143A, 78F1144A,
REF
/4 is selected as count clock to Figure 6-37 Example of
SUB
User's Manual U17854EJ9V0UD
μ
PD78F1142A(A),
μ
PD78F114xA)
(10/15)
Chapter
Throughout
INTRODUCTION
CHAPTER 1 OUTLINE
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 TIMER
ARRAY UNIT