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Figure 6-49. Example of Set Contents of Registers to Measure Input Pulse Interval
(a) Timer mode register 0n (TMR0n)
15
14
13
TMR0n
CKS0n
1/0
0
0
Operation clock selection
(b) Timer output register 0 (TO0)
Bit k
TO0
0: Outputs 0 from TO0k.
TO0k
0
(c) Timer output enable register 0 (TOE0)
Bit k
TOE0
0: Stops TO0k output operation by counting operation.
TOE0k
0
(d) Timer output level register 0 (TOL0)
Bit k
TOL0
0: Cleared to 0 when TOM0k = 0 (toggle mode).
TOL0k
0
(e) Timer output mode register 0 (TOM0)
Bit k
TOM0
0: Sets toggle mode.
TOM0k
0
Remark
n = 0 to 7, k = 0 to 6
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CHAPTER 6 TIMER ARRAY UNIT
12
11
10
9
MAS
CCS0n
STS0n2
STS0n1
STS0n0
TER0n
0
0
0
0
Capture trigger selection
001B: Selects the TI0k pin input valid edge.
Slave/master selection
0: Cleared to 0 when single-operation function is selected.
Count clock selection
0: Selects operation clock.
0: Selects CK00 as operation clock of channel n.
1: Selects CK01 as operation clock of channel n.
User's Manual U17854EJ9V0UD
8
7
6
5
4
CIS0n1
CIS0n0
1
1/0
1/0
0
0
Operation mode of channel n
010B: Capture mode
Setting of operation when counting is started
0: Does not generate INTTM0n when
counting is started.
1: Generates INTTM0n when counting is
started.
Selection of TI0k pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
3
2
1
0
MD0n3
MD0n2
MD0n1
MD0n0
0
1
0
1/0
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