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When the low-level is input to the RESET pin, the system is reset and each on-chip hardware is initialized to the
initial state.
When the RESET pin changes from low-level to high-level, the reset state is released and the CPU starts executing
the program. Initialize the contents of each register in the program as necessary.
13.1 Features
Analog noise elimination circuit (delay of approx. 60 ns) provided on reset pin
13.2 Pin Function
During the reset state, all the pins (except CLKOUT, RESET, X2, V
pins) are in the high-impedance state.
When an external memory is connected, a pull-up (or pull-down) resistor must be connected to each pin of ports
4, 5, 6, and 9. Otherwise, the memory contents may be lost if these pins go into a high-impedance state.
Also treat signal outputs of the on-chip peripheral I/O function and the output port so that they will not be affected.
In the ROM-less mode and single-chip mode 2, the CLKOUT signal is output even during the reset period (low
level output). In single-chip mode 1, the CLKOUT signal is not output until the PSC register is set. In the flash memory
programming mode, the CLKOUT signal is not output (low level output).
Table 13-1 shows the operating status of each pin during the reset period.
CHAPTER 13 RESET FUNCTION
User's Manual U11969EJ3V0UM00
, V
, CV
, CV
, AV
, AV
DD
SS
DD
SS
DD
and AV
SS
REF
377
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