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Instruction
Mnemonic
Operands
Group
8-bit data
MOV
A, [HL + byte]
transfer
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
word[B], #byte
A, word[B]
word[B], A
word[C], #byte
A, word[C]
word[C], A
word[BC], #byte
A, word[BC]
word[BC], A
[SP + byte], #byte
A, [SP + byte]
[SP + byte], A
B, saddr
B, !addr16
C, saddr
C, !addr16
X, saddr
X, !addr16
ES:!addr16, #byte
A, ES:!addr16
ES:!addr16, A
A, ES:[DE]
ES:[DE], A
ES:[DE + byte],#byte
A, ES:[DE + byte]
ES:[DE + byte], A
Notes 1.
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum.
CHAPTER 26 INSTRUCTION SET
Table 26-5. Operation List (2/17)
Bytes
Clocks
Note 1 Note 2
A ← (HL + byte)
2
1
4
−
(HL + byte) ← A
2
1
A ← (HL + B)
2
1
4
−
(HL + B) ← A
2
1
A ← (HL + C)
2
1
4
−
(HL + C) ← A
2
1
−
(B + word) ← byte
4
1
A ← (B + word)
3
1
4
−
(B + word) ← A
3
1
−
(C + word) ← byte
4
1
A ← (C + word)
3
1
4
−
(C + word) ← A
3
1
−
(BC + word) ← byte
4
1
A ← (BC + word)
3
1
4
−
(BC + word) ← A
3
1
(SP + byte) ← byte
−
3
1
−
A ← (SP + byte)
2
1
−
(SP + byte) ← A
2
1
−
B ← (saddr)
2
1
B ← (addr16)
3
1
4
−
C ← (saddr)
2
1
C ← (addr16)
3
1
4
X ← (saddr)
−
2
1
X ← (addr16)
3
1
4
−
(ES, addr16) ← byte
5
2
A ← (ES, addr16)
4
2
5
−
(ES, addr16) ← A
4
2
A ← (ES, DE)
2
2
5
−
(ES, DE) ← A
2
2
−
((ES, DE) + byte) ← byte
4
2
A ← ((ES, DE) + byte)
3
2
5
−
((ES, DE) + byte) ← A
3
2
User's Manual U17854EJ9V0UD
Operation
) selected by the system clock control
CLK
Flag
Z AC CY
689
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