NEC 78K0R/KE3 User Manual page 344

16-bit single-chip microcontrollers
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(3) Serial mode register mn (SMRmn)
SMRmn is a register that sets an operation mode of channel n. It is also used to select an operation clock
(MCK), specify whether the serial clock (SCK) may be input or not, set a start trigger, an operation mode (CSI,
2
UART, or I
C), and an interrupt source. This register is also used to invert the level of the receive data only in
the UART mode.
Rewriting SMRmn is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0 bit
can be rewritten during operation.
SMRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0020H.
Figure 11-6. Format of Serial Mode Register mn (SMRmn) (1/2)
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03),
F0154H, F0155H (SMR12), F0156H, F0157H (SMR13)
Symbol
15
14
SMRmn
CKS
CCS
mn
mn
CKS
mn
0
Operation clock CKm0 set by SPSm register
1
Operation clock CKm1 set by SPSm register
Operation clock MCK is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
higher 7 bits of the SDRmn register, a transfer clock (TCLK) is generated.
CCS
mn
0
Divided operation clock MCK specified by CKSmn bit
1
Clock input from SCK pin (slave transfer in CSI mode)
Transfer clock TCLK is used for the shift register, communication controller, output controller, interrupt controller,
and error controller. When CCSmn = 0, the division ratio of MCK is set by the higher 7 bits of the SDRmn register.
STS
mn
0
Only software trigger is valid (selected for CSI, UART transmission, and simplified I
1
Valid edge of R
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 to "0". Be sure to set bit 5 to "1".
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 12, 13
344
CHAPTER 11 SERIAL ARRAY UNIT
13
12
11
10
0
0
0
0
Selection of operation clock (MCK) of channel n
Selection of transfer clock (TCLK) of channel n
Selection of start trigger source
D pin (selected for UART reception)
X
User's Manual U17854EJ9V0UD
After reset: 0020H
9
8
7
6
5
0
STS
0
SIS
1
mn
mn0
R/W
4
3
2
1
0
0
MD
MD
mn2
mn1
2
C).
0
MD
mn0

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