NEC 78K0R/KE3 User Manual page 849

Function Details of
Function
Low- Used as interrupt
voltage (when detecting
detector level of supply
voltage (V ))
DD
(LVIOFF = 0)
Used as interrupt
(when detecting
level of input
voltage from
external input pin
(EXLVI))
Cautions for low-
voltage detector
APPENDIX B LIST OF CAUTIONS
Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the
LVIRF flag may become 1 from the beginning due to the power-on waveform.
For details of RESF, see CHAPTER 18 RESET FUNCTION.
The input voltage from the external input pin (EXLVI) must be EXLVI < V
In a system where the supply voltage (V
vicinity of the LVI detection voltage (V
how the low-voltage detector is used.
Operation example 1: When used as reset
The system may be repeatedly reset and released from the reset status.
The time from reset release through microcontroller operation start can be set
arbitrarily by the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each
system by means of a software counter that uses a timer, and then initialize the ports
(see Figure 20-11).
Operation example 2: When used as interrupt
Interrupt requests may be generated frequently.
Take the following action.
<Action>
Confirm that "supply voltage (V
falling edge of V , or "supply voltage (V
DD
the rising edge of V , in the servicing routine of the LVI interrupt by using bit 0
DD
(LVIF) of the low-voltage detection register (LVIM). Clear bit 1 (LVIIF) of interrupt
request flag register 0L (IF0L) to 0.
For a system with a long supply voltage fluctuation period near the LVI detection
voltage, take the above action after waiting for the supply voltage fluctuation time.
There is some delay from the time supply voltage (V
until the time LVI reset has been generated.
In the same way, there is also some delay from the time LVI detection voltage (V
≤ supply voltage (V
) until the time LVI reset has been released (see Figure 20-12).
DD
See the timing in Figure 20-2 (2) When LVI is ON upon power application (option
byte: LVIOFF = 0) for the reset processing time until the normal operation is entered
after the LVI reset is released.
User's Manual U17854EJ9V0UD
Cautions
) fluctuates for a certain period in the
DD
), the operation is as follows depending on
LVI
) ≥ detection voltage (V
)" when detecting the
DD LVI
) < detection voltage (V
DD
) < LVI detection voltage (V
DD
(25/33)
Page
p.645
μ
s
p.645
. p.647
DD
pp.649,
652
)" when detecting
LVI
) p.652
LVI
)
LVI
849