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Cautions 1. Be sure to clear bits 4 to 6 of IF1H and bits 1 to 7 of IF2H to 0.
2. When operating a timer, serial interface, or A/D converter after standby release, operate it
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory
manipulation instruction (CLR1). When describing in C language, use a bit manipulation
instruction such as "IF0L.0 = 0;" or "_asm("clr1 IF0L, 0");" because the compiled assembler
must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction
such as "IF0L &= 0xfe;" and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between "mov a, IF0L" and "mov IF0L, a", the flag is cleared
to 0 at "mov IF0L, a". Therefore, care must be exercised when using an 8-bit memory
manipulation instruction in C language.
(2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
MK0L, MK0H, MK1L, MK1H, MK2L, and MK2H can be set by a 1-bit or 8-bit memory manipulation instruction.
When MK0L and MK0H, MK1L and MK1H, and MK2L and MK2H are combined to form 16-bit registers MK0,
MK1, and MK2, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
584
CHAPTER 15 INTERRUPT FUNCTIONS
User's Manual U17854EJ9V0UD
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