NEC 78K0R/KE3 User Manual page 830

Function Details of
Function
Clock HIOTRM:
generator Internal-high-
speed oscillator
trimming register
−
X1/XT1
oscillator
Clock When LVI
generator default start
operation function stopped
when is set (option
power byte: LVIOFF =
supply 1)
voltage is
turned on
When LVI
default start
function enabled
is set (option
byte: LVIOFF =
0)
Controlling X1/P121,
high-speed X2/EXCLK/P122
system
X1 clock
clock
External main
system clock
830
APPENDIX B LIST OF CAUTIONS
The internal high-speed
increasing/decreasing the HIOTRM value to a value larger/smaller than a certain
value. A reversal, such
increasing/decreasing the HIOTRM value does not occur.
When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed
by the broken lines in the Figures 5-10 and 5-11 to avoid an adverse effect from
wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a
signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as V
Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power
consumption.
When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with
XT1, resulting in malfunctioning.
If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application
until the voltage reaches 1.8 V, input a low level to the RESET pin from power
application until the voltage reaches 1.8 V, or set the LVI default start function
stopped by using the option byte (LVIOFF = 0) (see Figure 5-14). By doing so, the
CPU operates with the same timing as <2> and thereafter in Figure 5-13 after reset
release by the RESET pin.
It is not necessary to wait for the oscillation stabilization time when an external clock
input from the EXCLK pin is used.
A voltage oscillation stabilization time is required after the supply voltage reaches
1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.07 V (TYP.) within
the power supply oscillation stabilization time, the power supply oscillation
stabilization time is automatically generated before reset processing.
It is not necessary to wait for the oscillation stabilization time when an external clock
input from the EXCLK pin is used.
The X1/P121 and X2/EXCLK/P122 pins are in the input port mode after a reset
release.
The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction. Therefore, it is necessary to also set the value of the
OSCSELS bit at the same time. For OSCSELS bit, see 5.6.3 Example of controlling
subsystem clock.
Set the X1 clock after the supply voltage has reached the operable voltage of the
clock to be used (see CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS)).
The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction. Therefore, it is necessary to also set the value of the
OSCSELS bits at the same time.
controlling subsystem clock.
User's Manual U17854EJ9V0UD
Cautions
oscillation frequency becomes
as the frequency becoming
For OSCSELS bits, see 5.6.3 Example of
(6/33)
Page
faster/slower by p.155
slower/faster by
p.157
.
SS
p.158
p.162
p.162
p.163
p.163
p.164
p.164
p.164
p.165