NEC 78K0R/KE3 User Manual page 338

Figure 11-2 shows the block diagram of serial array unit 1.
Peripheral enable
Serial clock select register 1 (SPS1)
register 0 (PER0)
PRS
SAU1EN
113
f
CLK
INTTM03
Channel 2
(LIN-bus supported)
Noise
elimination
Serial data input pin enabled/
disabled
(when UART3:RxD3/P14)
SNFEN30
TXE RXE DAP
12
12
Channel 3
(LIN-bus supported)
when UART3
Edge/level
detection
TXE RXE
DAP
13 13 13
338
CHAPTER 11 SERIAL ARRAY UNIT
Figure 11-2. Block Diagram of Serial Array Unit 1
0 0 1 1
0 0
PRS PRS PRS PRS PRS PRS PRS
112
111 110 103 102 101 100
4
4
Prescaler
0 11 f /2 0 - f /2
f /2 - f /2
CLK CLK
CLK CLK
Selector Selector
Serial data register 12 (SDR12)
CK11 CK10 (Clock division setting block)
MCK
CKS12 CCS12 STS12 MD122
Serial mode register 12 (SMR12)
CKP PTC PTC
EOC DIR SLC
12 12 121 120
12 12 121
Serial communication operation setting register 12 (SCR12)
Serial data register 13 (SDR13)
CK11 CK10 (Clock division setting block)
MCK
CKS13
CCS13 STS13 MD132
Serial mode register 13 (SMR13)
PTC
CKP EOC PTC DIR SLC
13 131 130
13 13 131
Serial communication operation setting register 13 (SCR13)
User's Manual U17854EJ9V0UD
Serial output register 1 (SO1)
0 0
0 0
1 1
11
(Buffer register block)
TCLK
Shift register
Communication controller
Mode selection
UART3
(for transmission)
MD121
TSF
SLC DLS BFF
DLS DLS
12 12
120 122 121 120
Serial status register 12 (SSR12)
(Buffer register block)
TCLK
Shift register
Communication controller
Mode selection
UART3
(for reception)
MD131
TSF BFF
SLC DSL DSL DSL
130 132 13 13
131 130
Serial status register 13 (SSR13)
Noise filter enable
register 0 (NFEN0)
SNFEN
1 SO12
1 1
30
Serial channel enable
SE13 SE12
0 0
status register 1 (SE1)
Serial channel start
SS13 SS12 0 0
register 1 (SS1)
Serial channel stop
ST13 ST12 0 0
register 1 (ST1)
Serial output enable
SOE12
0 0 0
register 1 (SOE1)
Serial output level
0 0 0
SOL12
register 1 (SOL1)
Output latch
PM14 or PM13
(P14 or p13)
Serial data output pin
(when UART3:TxD3/P13)
Output
controller
Interrupt
Serial transfer end interrupt
controller
(when UART3:INTST3)
Serial flag clear trigger
register 12 (SIR12)
FECT PECT OVCT
12 12 12
Clear
Error controller
Error
information
FEF PEF OVF
12
12 12
Interrupt
Serial transfer end interrupt
controller
(when UART3:INTSR3)
Serial flag clear trigger
register 13 (SIR13)
OVCT
FECT PECT
13 13 13
Clear
Error controller
Serial transfer error interrupt
(INTSRE3)
Error
information
OVF
FEF PEF
13 13 13