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(2) Serial interface: Serial array unit (2/18)
= −40 to +85°C, 1.8 V ≤ V
(T
A
<R>
(b) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
Parameter
SCKp cycle time
SCKp high-/low-level width
SIp setup time (to SCKp↑)
SIp hold time (from SCKp↑)
Delay time from SCKp↓ to
Note 4
SOp output
Notes 1.
The value must also be 4/f
2.
When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The SIp setup time becomes "to
SCKp↓" when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0.
3.
When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The SIp hold time becomes "from
SCKp↓" when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0.
4.
When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The delay time to SOp output becomes
"from SCKp↑" when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0.
5.
C is the load capacitance of the SCKp and SOp output lines.
Caution When using CSI10, select the normal input buffer for SI10 and the normal output mode for SO10 and
SCK10 by using the PIM0 and POM0 registers.
Remark p: CSI number (p = 00, 10), n: Channel number (n = 0, 2)
732
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
≤ 5.5 V, V
= EV
DD
DD
Symbol
4.0 V ≤ V
t
KCY1
2.7 V ≤ V
1.8 V ≤ V
4.0 V ≤ V
t
,
KH1
t
2.7 V ≤ V
KL1
1.8 V ≤ V
4.0 V ≤ V
Note 2
t
SIK1
2.7 V ≤ V
1.8 V ≤ V
Note 3
t
KSI1
t
C = 30 pF
KSO1
or more.
CLK
User's Manual U17854EJ9V0UD
= EV
= AV
= 0 V)
SS
SS
SS
Conditions
MIN.
≤ 5.5 V
Note 1
200
DD
Note 1
< 4.0 V
300
DD
Note 1
< 2.7 V
600
DD
≤ 5.5 V
/2 − 20
t
DD
KCY1
/2 − 35
< 4.0 V
t
DD
KCY1
/2 − 80
< 2.7 V
t
DD
KCY1
≤ 5.5 V
70
DD
< 4.0 V
100
DD
< 2.7 V
190
DD
30
Note 5
Standard Products
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
ns
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