Holtek HT32F54231 User Manual page 9

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Functional Descriptions ..................................................................................................... 287
Counter Mode ............................................................................................................................... 287
Clock Controller ............................................................................................................................ 291
Trigger Controller .......................................................................................................................... 292
Slave Controller ............................................................................................................................ 293
Master Controller .......................................................................................................................... 295
Channel Controller ........................................................................................................................ 296
Input Stage ................................................................................................................................... 299
Output Stage ................................................................................................................................. 301
Update Management .................................................................................................................... 312
Single Pulse Mode ........................................................................................................................ 314
Asymmetric PWM Mode ............................................................................................................... 316
Timer Interconnection ................................................................................................................... 317
Trigger Peripheral Start................................................................................................................. 321
Lock Level Table ........................................................................................................................... 321
PDMA Request (HT32F54243/HT32F54253 only) ....................................................................... 322
Register Map ..................................................................................................................... 323
Register Descriptions ......................................................................................................... 324
Timer Counter Configuration Register - CNTCFR ....................................................................... 324
Timer Mode Configuration Register - MDCFR ............................................................................. 325
Timer Trigger Configuration Register - TRCFR ............................................................................ 328
Timer Control Register - CTR ...................................................................................................... 329
Channel 0 Input Configuration Register - CH0ICFR .................................................................... 330
Channel 1 Input Configuration Register - CH1ICFR .................................................................... 332
Channel 2 Input Configuration Register - CH2ICFR .................................................................... 334
Channel 3 Input Configuration Register - CH3ICFR .................................................................... 336
Channel 0 Output Configuration Register - CH0OCFR ............................................................... 338
Channel 1 Output Configuration Register - CH1OCFR ............................................................... 340
Channel 2 Output Configuration Register - CH2OCFR ............................................................... 342
Channel 3 Output Configuration Register - CH3OCFR ............................................................... 344
Channel Control Register - CHCTR ............................................................................................. 346
Channel Polarity Configuration Register - CHPOLR .................................................................... 348
Channel Break Configuration Register - CHBRKCFR ................................................................. 349
Channel Break Control Register - CHBRKCTR ........................................................................... 350
Timer PDMA/Interrupt Control Register - DICTR ......................................................................... 352
Timer Event Generator Register - EVGR ..................................................................................... 354
Timer Interrupt Status Register - INTSR ...................................................................................... 356
Timer Counter Register - CNTR................................................................................................... 358
Timer Prescaler Register - PSCR ................................................................................................ 359
Timer Counter-Reload Register - CRR ........................................................................................ 360
Timer Repetition Register - REPR ............................................................................................... 360
Channel 0 Capture/Compare Register - CH0CCR ...................................................................... 361
Channel 1 Capture/Compare Register - CH1CCR ...................................................................... 361
Channel 2 Capture/Compare Register - CH2CCR ...................................................................... 362
Channel 3 Capture/Compare Register - CH3CCR ...................................................................... 363
Rev. 1.00 9 of 576 January 28, 2022