Trigger Peripheral Start; Lock Level Table; Table 37. Lock Level Table - Holtek HT32F54231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253

Trigger Peripheral Start

To interconnect to the peripherals, such as ADC, Timer and so on, the MCTM can output the MTO
signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as a peripheral
input trigger signal, depending on the MCU specification.

Lock Level Table

In addition to the break input and output management, a write protection has been internally
implemented in the break circuitry to safeguard the application. Users can choose one protection
level selected by the LOCKLV bits to protect the relative control bits of the registers. The LOCKLV
bits can only be written once after an MCTM or system reset. Then the protected bits will be
locked and cannot be changed until an MCTM reset or system reset occurs.

Table 37. Lock Level Table

Lock Configuration
Lock Level 1 (LOCKLV = "01") CHDTG
Lock Level 2 (LOCKLV = "10")
Lock Level 3 (LOCKLV = "11")
Notes: 1. The MCTMEN bit of the APBCCR1 register is located in the CKCU unit and used to control
the clock source of the MCTM unit.
2. The CKMEN bit of the GCCR register is located in the CKCU unit and used to monitor the
high speed external clock (HSE) source. If the CKMEN bit is enabled and when hardware
detects HSE clock stuck at low/high state, internal hardware will automatically switch the
system clock to internal high speed RC clock (HSI) to protect the system safety.
3. When the MCTMEN and CKMEN control bits of the CKCU lock protection mode is enabled
in the MCTM unit, the bits will be allowed to enable only and inhibited to disable again.
Rev. 1.00
Protected Bits
CHxOIS CHxOISN BKE
CHDTG CHxOIS CHxOISN BKE
CHxP CHxNP CHOSSI
CHDTG CHxOIS CHxOISN BKE
CHxP CHxNP CHOSSI
CHxPRE CHxOM
321 of 576
BKP CHAOE
BKP CHAOE
CHOSSR MCTMEN (1) CKMEN
BKP CHAOE
CHOSSR MCTMEN CKMEN
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January 28, 2022
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