Holtek HT32F54231 User Manual page 8

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Master Controller .......................................................................................................................... 231
Channel Controller ........................................................................................................................ 232
Input Stage ................................................................................................................................... 234
Quadrature Decoder ..................................................................................................................... 236
Output Stage ................................................................................................................................. 237
Update Management .................................................................................................................... 241
Single Pulse Mode ........................................................................................................................ 242
Asymmetric PWM Mode ............................................................................................................... 244
Timer Interconnection ................................................................................................................... 244
Trigger Peripherals Start ............................................................................................................... 247
PDMA Request (HT32F54243/HT32F54253 only) ....................................................................... 247
Register Map ..................................................................................................................... 248
Register Descriptions ......................................................................................................... 249
Timer Counter Configuration Register - CNTCFR ....................................................................... 249
Timer Mode Configuration Register - MDCFR ............................................................................. 250
Timer Trigger Configuration Register - TRCFR ............................................................................ 253
Timer Control Register - CTR ...................................................................................................... 254
Channel 0 Input Configuration Register - CH0ICFR .................................................................... 255
Channel 1 Input Configuration Register - CH1ICFR .................................................................... 256
Channel 2 Input Configuration Register - CH2ICFR .................................................................... 258
Channel 3 Input Configuration Register - CH3ICFR .................................................................... 259
Channel 0 Output Configuration Register - CH0OCFR ............................................................... 261
Channel 1 Output Configuration Register - CH1OCFR ............................................................... 263
Channel 2 Output Configuration Register - CH2OCFR ............................................................... 265
Channel 3 Output Configuration Register - CH3OCFR ............................................................... 267
Channel Control Register - CHCTR ............................................................................................. 269
Channel Polarity Configuration Register - CHPOLR .................................................................... 270
Timer PDMA/Interrupt Control Register - DICTR ......................................................................... 271
Timer Event Generator Register - EVGR ..................................................................................... 272
Timer Interrupt Status Register - INTSR ...................................................................................... 274
Timer Counter Register - CNTR................................................................................................... 276
Timer Prescaler Register - PSCR ................................................................................................ 277
Timer Counter-Reload Register - CRR ........................................................................................ 278
Channel 0 Capture/Compare Register - CH0CCR ...................................................................... 279
Channel 1 Capture/Compare Register - CH1CCR ...................................................................... 280
Channel 2 Capture/Compare Register - CH2CCR ...................................................................... 281
Channel 3 Capture/Compare Register - CH3CCR ...................................................................... 282
Channel 0 Asymmetric Compare Register - CH0ACR ................................................................. 283
Channel 1 Asymmetric Compare Register - CH1ACR ................................................................. 283
Channel 2 Asymmetric Compare Register - CH2ACR ................................................................. 284
Channel 3 Asymmetric Compare Register - CH3ACR ................................................................. 284
15 Motor Control Timer (MCTM) ........................................................................... 285
Introduction ........................................................................................................................ 285
Features ............................................................................................................................. 286
Rev. 1.00 8 of 576 January 28, 2022