32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Starting two timers synchronously in response to an external trigger
Configure MCTM to operate in the master mode to send its enable signal as a trigger output
▆
(MMSEL = 0x1).
Configure MCTM slave mode to receive its input trigger source from MT_CH0 pin (TRSEL = 0x1).
▆
Configure MCTM to be in the slave trigger mode (SMSEL = 0x6).
▆
Enable the MCTM master timer synchronisation function by setting the TSE bit in the MDCFR
▆
register to 1 to synchronise the slave timer.
Configure GPTM to receive its input trigger source from the MCTM trigger output (TRSEL = 0xA).
▆
Configure GPTM to be in the slave trigger mode (SMSEL = 0x6).
▆
Master MCTM
MCTM (TME bit)
MCTM (TEVIF)
MCTM CK_PSC
Slave GPTM
GPTM (TME bit)
GPTM (TEVIF)
GPTM CK_PSC
Figure 113. Trigger MCTM and GPTM with the MCTM CH0 Input
Rev. 1.00
f
= f
DTS
CLKIN
TI0
TI0FP
TI0S0ED
MCTM CNTR
34
Write UEV1G bit
GPTM CNTR
11
319 of 576
TSE=1
Delay
0
1
2
ITI
0
1
2
0
Write UEVG bit
3
4
5
3
4
5
January 28, 2022
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