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Features
·
Operating voltage:
f
=4MHz: 2.2V~5.5V
SYS
f
=8MHz: 3.3V~5.5V
SYS
·
32 bidirectional I/O lines
·
Two external interrupt inputs
·
Dual 16-bit programmable timer/event counters with
Programmable Frequency Divider, PFD, function
·
Single 8-bit programmable timer/event counter with
source clock prescaler
·
47´3 or 46´4 segment LCD driver with logic
output option for SEG0~SEG23)
·
32K´16 program memory
·
768´8 data memory RAM
·
Universal Asynchronous Receiver Transmitter
-UART
·
PFD function for sound generation
·
Real Time Clock - RTC
·
8-bit RTC prescaler
General Description
The HT46RU67/HT46CU67 are 8-bit, high perfor-
mance, RISC architecture microcontroller devices spe-
cifically designed for A/D product applications that
interface directly to analog signals and which require an
LCD Interface. The HT46CU67, mask version device, is
fully pin and functionally compatible with its sister
HT46RU67 OTP device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, multi-channel A/D
Rev. 1.30
HT46RU67/HT46CU67
A/D Type 8-Bit MCU with LCD
·
Watchdog Timer
·
Buzzer output function
·
Crystal, RC and 32768Hz crystal system oscillator
option
·
Power down and wake-up functions reduce power
consumption
·
16-level subroutine nesting
·
8-channel 12-bit resolution A/D converter
·
4-channel PWM outputs shared with 4 I/O lines
·
SIO - Synchronous serial I/O - function
·
Bit manipulation instruction
·
16-bit table read instruction
·
Up to 0.5ms instruction cycle with 8MHz system clock
·
63 powerful instructions
·
Instruction execution within 1 or 2 machine cycles
·
Low voltage reset/detector function
·
100-pin LQFP package
Converter, Pulse Width Modulation function, UART, se-
rial I/O interface, Power Down and Wake-up functions,
in addition to a flexible and configurable LCD interface
enhance the versatility of these devices to control a
wide range of applications requiring analog signal pro-
cessing and LCD interfacing, such as electronic meter-
ing, environmental monitoring, handheld measurement
tools, motor driving, etc. for both the industrial and home
appliance application areas.
1
June 10, 2014
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Table of Contents
Related Manuals for Holtek HT46RU67
Summary of Contents for Holtek HT46RU67
- Page 1 100-pin LQFP package · 8-bit RTC prescaler General Description The HT46RU67/HT46CU67 are 8-bit, high perfor- Converter, Pulse Width Modulation function, UART, se- mance, RISC architecture microcontroller devices spe- rial I/O interface, Power Down and Wake-up functions, cifically designed for A/D product applications that...
- Page 2 HT46RU67/HT46CU67 Block Diagram Rev. 1.30 June 10, 2014...
- Page 3 HT46RU67/HT46CU67 Pin Assignment H T 4 6 R U 6 7 / H T 4 6 C U 6 7 1 0 0 L Q F P - A Rev. 1.30 June 10, 2014...
- Page 4 HT46RU67/HT46CU67 Pin Description Configuration Pin Name Description Option Bidirectional 8-bit input/output port. Each individual pin on this port can PA0/BZ Pull-high be configured as a wake-up input by a configuration option. Software in- PA1/BZ Wake-up structions determine if the pin is a CMOS output or Schmitt Trigger input.
- Page 5 HT46RU67/HT46CU67 Configuration Pin Name Description Option An LCD duty-cycle configuration option determines if SEG46 is config- COM0~COM2 1/3 or 1/4 Duty ured as a segment driver or as a common output driver for the LCD COM3/SEG46 COM3 or SEG46 panel. COM0~COM2 are the LCD common outputs.
- Page 6 HT46RU67/HT46CU67 Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions ¾ No load, system HALT, Standby Current LCD On at HALT, C type, STB2 =RTC OSC) ¾ UART Off ¾ No load, system HALT, Standby Current LCD On at HALT, C type,...
- Page 7 HT46RU67/HT46CU67 Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions ¾ LCD Common and Segment =0.1V Current ¾ -160 ¾ LCD Common and Segment =0.9V Current -180 -360 ¾ ¾ Pull-high Resistance of I/O Ports ¾ and INT0, INT1 ¾...
- Page 8 HT46RU67/HT46CU67 Functional Description Program Counter - PC Execution Flow The system clock is derived from either a crystal or an The program counter is 15 bits wide and controls the se- RC oscillator or a 32768Hz crystal oscillator. It is inter- quence in which the instructions stored in the program nally divided into four non-overlapping clocks.
- Page 9 HT46RU67/HT46CU67 microcontroller manages program control by loading the Certain locations in the Program Memory are reserved required address into the Program Counter. For condi- for special usage: tional skip instructions, once the condition has been · Location 000H met, the next instruction, which has already been Location 000H is reserved for program initialisation.
- Page 10 HT46RU67/HT46CU67 · Location 010H nor part of the program, and is neither readable nor Location 010H is reserved for the Timer/Event Coun- writeable. Its activated level is indexed by a stack ter 1 interrupt service program. If a timer interrupt re-...
- Page 11 HT46RU67/HT46CU67 Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write op- eration of [00H] and [02H] accesses the Data Memory pointed to by MP0 and MP1 respectively. Reading loca- tion 00H or 02H indirectly returns the result 00H. Writing to it indirectly results to no operation.
- Page 12 HT46RU67/HT46CU67 Bit No. Label Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise C is cleared. C is also affected by a ro- tate through carry instruction.
- Page 13 HT46RU67/HT46CU67 The UART Bus interrupt is initialized by setting the MFIC register, caused by a regular real time clock UART Bus interrupt request flag, URF; bit 5 of the time-out, RTF; bit 6 of the MFIC register or caused by a INTC1 register, caused by transmit data register empty time base time-out, TBF;...
- Page 14 HT46RU67/HT46CU67 that is caused by a complete reception or transmission bit 4 of the MFIC register, the real time clock interrupt of 8-bits of data from or to the serial interface. After the flag, RTF; bit 6 of the MFIC register, the time base inter- interrupt is enabled, and the stack is not full and the SIF rupt flag, TBF;...
- Page 15 HT46RU67/HT46CU67 If the crystal oscillator is to be used, a crystal across give a time of about 2.1s~4.3s for the internal WDT os- OSC1 and OSC2 is needed to provide the feedback and cillator. If the WDT oscillator is disabled, the WDT clock phase shift required for oscillation, no other external may still come from the instruction clock.
- Page 16 HT46RU67/HT46CU67 Power Down Operation - HALT Time Base The Power Down mode is initialised by the ²HALT² in- The time base offers a periodic time-out period to gener- ate a regular internal interrupt. Its time-out period struction and results in the following.
- Page 17 HT46RU67/HT46CU67 Reset The functional unit chip reset status is shown below. There are several ways in which a reset may occur. Program Counter 000H · RES is reset during normal operation Interrupt Disabled · Power on reset Prescaler, Divider Cleared ·...
- Page 18 HT46RU67/HT46CU67 The register states are summarized below: Reset WDT Time-out RES Reset RES Reset WDT Time-out Register (Power On) (Normal Operation) (Normal Operation) (HALT) (HALT)* xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx xxxx uuuu uuuu uuuu uuuu...
- Page 19 HT46RU67/HT46CU67 Reset WDT Time-out RES Reset RES Reset WDT Time-out Register (Power On) (Normal Operation) (Normal Operation) (HALT) (HALT)* UCR1 0000 00x0 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu UCR2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu...
- Page 20 HT46RU67/HT46CU67 The overflow of the Timer/Event Counter 0/1/2 is one of ting the timer enable bit high together with a mode bit the wake-up sources. The Timer/Event Counter 0/1 can modification, may lead to improper timer operation if ex- also be applied to a PFD or Programmable Frequency...
- Page 21 HT46RU67/HT46CU67 Timer/Event Counter 2 PFD Source Option Bit No. Label Function Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0= 000: f 001: f T0PSC0 010: f T0PSC1 011: f T0PSC2 100: f 101: f 110: f 111: f /128 Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1:count on falling edge;...
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Page 22: Table Of Contents
HT46RU67/HT46CU67 Bit No. Label Function ¾ Unused bit, read as ²0² Defines the TMR1 active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge;... - Page 23 HT46RU67/HT46CU67 Input/Output Ports the pull-high configuration options. Each bit of these in- put/output latches can be set or cleared by the ²SET There are 32 bidirectional input/output lines in the device, [m].i² and ²CLR [m].i² bit manipulation instructions. labeled as PA, PB, PC and PD, which are mapped to the...
- Page 24 HT46RU67/HT46CU67 Port PB can also be used as A/D converter inputs. There is a PWM function shared with PD0/PD1/PD2/PD3. If the PWM function is enabled, the PWM0/PWM1/PWM2/ PWM3 signal will appear on PD0/PD1/PD2/PD3, if PD0/ PD1/ PD2/PD3 are operating in output mode. Writing ²1² to the PD0~PD3 data register will enable the PWM output function while writing ²0²...
- Page 25 HT46RU67/HT46CU67 PC6/TX Input/Output Ports PC7/RX Input/Output Ports Pulse Width Modulator duty cycle of one modulation cycle of the output wave- form, should be placed. To increase the PWM modula- Each devices is provided with either three or four Pulse tion frequency, each modulation cycle is subdivided into...
- Page 26 HT46RU67/HT46CU67 For all devices, the PWM clock source is the system clock f Package Channels PWM Mode Output Pin PWM Register Name PWM0/PWM1/PWM2/PWM3 100-pin 6+2 or 7+1 PD0/PD1/PD2/PD3 PWM Function Table four individual sub-cycles known as modulation cycle This method of dividing the original modulation cycle 0 ~ modulation cycle 3, denoted as ²i²...
- Page 27 HT46RU67/HT46CU67 · 7+1 PWM mode Parameter AC (0~1) Duty Cycle Each full PWM cycle, as it is controlled by an 8-bit DC + 1 i<AC PWM register, has 256 clock periods. However, in the Modulation cycle i 7+1 PWM mode, each PWM cycle is subdivided into...
- Page 28 HT46RU67/HT46CU67 The following sample program shows how the PWM outputs are setup and controlled, the corresponding PWM out- put configuration option must first be selected. clr PDC.0 ; set pin PD0 as output clr PDC.1 ; set pin PD1 as output clr PDC.2...
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Page 29: Bit No
HT46RU67/HT46CU67 Bit No. Label Function Selects the A/D converter clock source 00=system clock/2 ADCS0 01=system clock/8 ADCS1 10=system clock/32 11=undefined ¾ Unused bit, read as ²0² TEST For test mode used only ACSR (27H) Register Bit No. Label Function ACS2, ACS1, ACS0: Select A/D channel... - Page 30 HT46RU67/HT46CU67 The following programming example illustrates how to setup and implement an A/D conversion. The method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete. Example: using EOCB Polling Method to detect end of conversion...
- Page 31 HT46RU67/HT46CU67 LCD Memory and written to only by indirect addressing mode using MP1. When data is written into the LCD display mem- The device provides an area of embedded data memory ory, it is automatically read by the LCD driver which then for LCD display.
- Page 32 HT46RU67/HT46CU67 D u r i n g a R e s e t P u l s e N o r m a l O p e r a t i o n M o d e H A L T M o d e LCD Driver Output (1/3 Duty, 1/2 Byte, R/C Type) Rev.
- Page 33 HT46RU67/HT46CU67 LCD Driver Output Rev. 1.30 June 10, 2014...
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Page 34: Unused Bit, Read As ²0²
HT46RU67/HT46CU67 Low Voltage Reset/Detector Functions There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in this microcontroller. These two functions can be enabled/disabled by options. Once the LVD option is enabled, the user can use the RTCC.3 bit to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5, otherwise, the LVD function is... - Page 35 I/O pin, if the pin is not configured as a receiver, which occurs The HT46RU67/HT46CU67 devices contain an inte- if the RXEN bit in the UCR2 register is equal to zero.
- Page 36 HT46RU67/HT46CU67 · USR register RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR reg- The USR register is the status register for the UART, ister, and if the RXR register has no data available.
- Page 37 HT46RU67/HT46CU67 ¨ used, if the bit is equal to ²0² then only one stop bit is PERR used. The PERR flag is the parity error flag. When this read only flag is ²0² it indicates that a parity error ¨...
- Page 38 HT46RU67/HT46CU67 · to ²0² and if the MCU is in the Power Down Mode, UCR2 register any edge transitions on the RX pin will not wake-up The UCR2 register is the second of the two UART control registers and serves several purposes. One of the device.
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Page 39: Sys /2
HT46RU67/HT46CU67 ¨ TXEN By programming the BRGH bit which allows selection of the related formula and programming the required The TXEN bit is the Transmitter Enable Bit. When this bit is equal to ²0² the transmitter will be disabled value in the BRG register, the required baud rate can be setup. - Page 40 HT46RU67/HT46CU67 Baud Rates for BRGH=1 Baud Rate =4MHz =3.579545MHz K/BPS Kbaud Error (%) Kbaud Error (%) ¾ ¾ ¾ ¾ ¾ ¾ 1.202 0.16 1.203 0.23 2.404 0.16 2.406 0.23 4.808 0.16 4.76 -0.83 9.615 0.16 9.727 1.32 19.2 19.231 0.16...
- Page 41 HT46RU67/HT46CU67 ¨ Transmitting data Start Data Address Parity Stop When the UART is transmitting data, the data is Bits Bits Bits shifted on the TX pin from the shift register, with the Example of 8-bit Data Formats least significant bit first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register.
- Page 42 HT46RU67/HT46CU67 ¨ Transmit break Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin and not as an I/O pin. If the TXBRK bit is set then break characters will be sent on the next transmission. Break character At this point the receiver will be enabled which will transmission consists of a start bit, followed by 13´...
- Page 43 HT46RU67/HT46CU67 ¨ Receiver interrupt rises at the same time as the RXIF bit which itself generates an interrupt. The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. Note that the NF flag is reset by a USR register read...
- Page 44 HT46RU67/HT46CU67 while the two receiver interrupt conditions have a mode is enabled, then to ensure correct operation, the shared enable bit. These enable bits can be used to parity function should be disabled by resetting the par- mask out individual UART interrupt sources.
- Page 45 HT46RU67/HT46CU67 Serial Interface Serial interface function has four basic signals included. They are SDI (serial data input), SDO (serial data output), SCK (serial clock) and SCS (slave select pin). Note: SCS can be named SCS in the design note. ¨...
- Page 46 HT46RU67/HT46CU67 Clock polarity= rising (CLK) or falling (CLK): 1 or 0 (mask option) Modes Operations Select CKS and select M1, M0 = 00,01,10 Select CSEN, MLS (the same as the slave) Set SBEN Writing data to SBDR ® data is stored in TXRX buffer ® output CLK (and SCS) signals ® go to step 5 ®...
- Page 47 HT46RU67/HT46CU67 Rev. 1.30 June 10, 2014...
- Page 48 HT46RU67/HT46CU67 Options The following shows the options in the device. All these options should be defined in order to ensure having a proper functioning system. Options OSC type selection. This option is to determine if an RC or crystal or 32768Hz crystal oscillator is chosen as system clock.
- Page 49 HT46RU67/HT46CU67 Options PFD selection. If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 re- spectively.
- Page 50 HT46RU67/HT46CU67 Application Circuits R e s e t C i r c u i t R C S y s t e m O s c i l l a t o r C r y s t a l / R e s o n a t o r...
- Page 51 For easier understanding of the various instruction The standard logical operations such as AND, OR, XOR codes, they have been subdivided into several func- and CPL all have their own instruction within the Holtek tional groupings. microcontroller instruction set. As with the case of most...
- Page 52 In addition to the above functional instructions, a range of other instructions also exist such as the ²HALT² in- ory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for struction for Power-down operations and instructions to...
- Page 53 HT46RU67/HT46CU67 Mnemonic Description Cycles Flag Affected Rotate RRA [m] Rotate Data Memory right with result in ACC None Note RR [m] Rotate Data Memory right None RRCA [m] Rotate Data Memory right through Carry with result in ACC Note RRC [m]...
- Page 54 HT46RU67/HT46CU67 Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ¬ ACC + [m] + C...
- Page 55 HT46RU67/HT46CU67 CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then in- crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address.
- Page 56 HT46RU67/HT46CU67 CPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ¬ [m] Operation Affected flag(s) CPLA [m]...
- Page 57 HT46RU67/HT46CU67 INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. [m] ¬ [m] + 1 Operation Affected flag(s) INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu- lator.
- Page 58 HT46RU67/HT46CU67 OR A,x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op- eration. The result is stored in the Accumulator. ACC ¬ ACC ²OR² x Operation Affected flag(s)
- Page 59 HT46RU67/HT46CU67 RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0.
- Page 60 HT46RU67/HT46CU67 SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are sub- tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
- Page 61 HT46RU67/HT46CU67 SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction.
- Page 62 HT46RU67/HT46CU67 SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 « [m].7 ~ [m].4 Operation Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
- Page 63 HT46RU67/HT46CU67 XOR A,[m] Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op- eration. The result is stored in the Accumulator. ACC ¬ ACC ²XOR² [m] Operation Affected flag(s)
- Page 64 HT46RU67/HT46CU67 Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information.
- Page 65 HT46RU67/HT46CU67 100-pin LQFP (14mm´14mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. ¾ ¾ 0.630 BSC ¾ ¾ 0.551 BSC ¾ ¾ 0.630 BSC ¾ ¾ 0.551 BSC ¾ ¾ 0.020 BSC 0.007 0.009 0.011 0.053 0.055 0.057 ¾...
- Page 66 Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification.
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